Video and Vision Processing Suite
The Intel® FPGA Video and Vision Processing Suite is a collection of next-generation Intel® FPGA intellectual property (IP) funct…
- Video Processing
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Video and Vision Processing Suite
The Intel® FPGA Video and Vision Processing Suite is a collection of next-generation Intel® FPGA intellectual property (IP) funct…
Forward-error correction (FEC) channel codes commonly improve the energy efficiency of wireless communication systems.
Tone Mapping Operator (TMO) Intel® FPGA IP
As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the Tone Mapping Operator (TMO) Intel® FPGA IP corrects …
Reed Solomon II Intel® FPGA IP Core
The Reed Solomon II Intel® FPGA intellectual property (IP) core offers a fully parameterizable Reed Solomon encoder and decoder.
The Reed-Solomon (RS) compiler offers a fully parameterizable RS coder and RS decoder.
A numerically controlled oscillator (NCO) is a digital signal generator, which synthesizes a discrete-time, discrete-valued repre…
High-Speed Reed Solomon Intel® FPGA IP Core
The High-Speed Reed Solomon Intel® FPGA intellectual property (IP) core uses a large parallel architecture to achieve a large thr…
The FIR II Intel IP core provides a fully-integrated finite impulse response (FIR) filter function optimized for use with Intel F…
The Fast Fourier transform (FFT) Intel FPGA intellectual property (IP) core is a high-performance, parameterizable FFT processor.
The CIC Intel FPGA IP core implements a Cascaded integrator-comb (CIC) filter with data ports that are compatible with the Avalon…
The Bose, Chaudhuri, and Hocquenghem (BCH) error correction intellectual property (IP) core is typically used in NAND flash appli…
The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with t…
Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy…
Siemens EDA* AXI Verification IP Suite
The Siemens EDA AXI Verification IP Suite (Intel® FPGA Edition) provides bus functional models (BFMs) to simulate the behavior an…
Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
PQCryptoLib-Embedded is a versatile, CAVP-ready cryptography library designed and optimized for embedded devices.
xSPI Multiple Bus Memory Controller
The industry ‘defacto standard’ memory controller for xSPI-like memories: HyperBus™ 1.0, 2.0 and 3.0 – OctaBus™ – Xccela® Bus – O…
Filtering with packet payload scanning Message filters are placed in the middle of a TCP / TLS session to scan application data, …
Secure protocol communication by hardware Our SSL/TLS engine accelerates and offloads processing for encryption / decryption and …
Full hardware TCP/UDP protocol stack realize both high performance and guaranteed delivery Our TCP/UDP offload engine supports si…
The Lancero JPEG-LS Lossless Image Encoder for FPGAs is an efficient implementation of the best-in-class lossless image compressi…