Altera
•
HQ:
USA
The MACsec Intel® FPGA IP core implements the IEEE Media Access Control Security standard as defined in 802.1AE (2018) as fully c…
- MACsec
Compare 18,300 Semiconductor IP Cores from 472 vendors
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Low Latency Ethernet 10G MAC FPGA IP
Altera• HQ: USAThe Low Latency Ethernet 10G MAC FPGA IP core (soft IP) offers low round-trip latency, and an efficient resource footprint.
- Ethernet
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Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core
Altera• HQ: USAIntel® offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet Intel® FPGA IP core targe…
- Single-Protocol PHY
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Altera• HQ: USA
The JEDEC committee created the JESD204 data converter serial interface standard to standardize and reduce the number of data inp…
- JESD204
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Altera• HQ: USA
The Interlaken Intel® FPGA IP core is Interlaken Protocol Definition v1.2 compliant and allows system developers to achieve high …
- Interlaken
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Interlaken Look-Aside Intel® FPGA IP
Altera• HQ: USAInterlaken Look-Aside is a scalable protocol that allows interoperability between a datapath device and a look-aside coprocessor …
- Interlaken
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Altera• HQ: USA
The enhanced Common Public Radio Interface (eCPRI) Altera® FPGA IP core implements the eCPRI specification version 2.0.
- CPRI
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Compute Express Link (CXL) FPGA IP
Altera• HQ: USAIndustry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.
- CXL
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Altera• HQ: USA
The Common Public Radio Interface (CPRI) Altera® FPGA IP core implements the CPRI Specification V7.0.
- CPRI
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Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core
Altera• HQ: USAThe Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instant…
- Single-Protocol PHY
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Intel® Agilex™ 7 F-Tile Ethernet Hard IP
Altera• HQ: USAThe Intel® Agilex™ 7 FPGA F-Tile incorporates a fracturable, configurable, hardened Ethernet protocol stack for supporting rates …
- Ethernet
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Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile Hard IP
Altera• HQ: USAThe Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible …
- Multi-Protocol PHY
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Altera• HQ: USA
The 50G Ethernet Intel® FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Cons…
- Ethernet
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40G Ethernet MAC and PHY FPGA IP Core
Altera• HQ: USAThe 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010.
- Single-Protocol PHY
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Altera• HQ: USA
This IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium.
- Ethernet
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1G/10Gb Ethernet PHY Intel® FPGA IP
Altera• HQ: USAThe 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding s…
- Single-Protocol PHY
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Multi-Rate Ethernet PHY FPGA IP
Altera• HQ: USAThe Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device re…
- Single-Protocol PHY
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Altera• HQ: USA
The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection.
- Single-Protocol PHY
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Altera• HQ: USA
The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implem…
- Channel Coding
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Altera• HQ: USA
As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the Warp Intel® FPGA IP provides a optimized solution fo…
- Video Processing