High-Performance, Configurable, 8-bit Microcontroller
The R8051XC2 configurable processor core implements a range of fast, 8-bit, micro-controllers that execute the MCS®51 instruction…
- MCU
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
High-Performance, Configurable, 8-bit Microcontroller
The R8051XC2 configurable processor core implements a range of fast, 8-bit, micro-controllers that execute the MCS®51 instruction…
Low-Power Bandgap Reference Circuit - UMC 0.09um
High precision Bandgap Reference Circuit with very low Power consumption of less than 10µA
TC1700 is a FEC receiver adressing LTE, LTE-A, WiMAX, HSPA/+, and legacy 3G standard.
PSI2488-U9 is a GPON ONT SERDES capable of receiving serial data at the rate of 2.488Gbps and transmitting data at the rate of 1.…
Audio PLL - Fractional-N ±0.05 ppm accuracy
This PLL can generate all the frequencies used by audio systems from a stable clock of 10 to 40Mhz.
Common Scrambling Algorithm IP core
The Helion DVB-CSA cores implement the ETSI specified Common Scrambling Algorithm (CSA) which is used to provide the conditional …
3GPP LTE 3GPP2 1xEV-DO Turbo Decoder with Ping Pong Input and Output Memories
This is a fully compatible 3GPPTM LTE and 3GPP2 1xEV-DO Release B turbo decoder with ping-pong input and output memories.
Great River's ARINC 818 IP Core provides an easy way to implement ARINC 818–compliant interfaces in Xilinx and Altera PLDs.
VeriSilicon SMIC 0.18¦Ìm 1.8V/3.3V ANALOGIO_DUP_05 IO Library
VeriSilicon SMIC 0.18um 1.8V/3.3V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturin…
VeriSilicon SMIC 0.13¦Ìm 1.2V/3.3V DUPIO_01 Library
VeriSilicon SMIC 0.13¦Ìm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing Int…
VeriSilicon SMIC 0.13¦Ìm 1.2V/2.5V DUPIO_01 Library
VeriSilicon SMIC 0.13¦Ìm 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing Int…
VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO Library
VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturin…
VeriSilicon SMIC 0.13¦Ìm 1.2V/3.3V ANALOGIO_DUP_05 IO Library
VeriSilicon SMIC 0.13um 1.2V/3.3V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturin…
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufactur…
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufactur…
cjTAG IEEE 1149.7 Compact TAP Controller
The Compact TAP IP from Silvaco provides an IEEE 1149.7-compliant Test Access Port (TAP), enabling you to take advantage of IEEE …
Super-Speed USB3.0 Hub Controller
USB3.0 SuperSpeed Hub The Super Speed USB bus is implemented as a separate dual-simplex data path consisting of two uni-direction…
Super-speed USB3.0 Device Controller
USB3.0 SuperSpeed Device The Super Speed USB bus is implemented as a separate dual-simplex data path consisting of two uni-direct…
High Throughput Additive White Gaussian Noise Generator
A configurable AWGN generator that can be used as emulator of a noisy transmission channel and can support very high throughput r…
Classification and Forwarding Engine
Innovaide provides a comprehensive intelligent solution for Next Generation Carrier Ethernet.