1.8V Fault Tolerant General Purpose I/O Inline Pad Set
The 1.8V GPIO FT library provides ultra low leakage general purpose bidirectional I/O cells.
- GlobalFoundries
- 22nm
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
1.8V Fault Tolerant General Purpose I/O Inline Pad Set
The 1.8V GPIO FT library provides ultra low leakage general purpose bidirectional I/O cells.
1.8V Fault Tolerant General Purpose I/O Staggered Pad Set
The 1.8V GPIO FT library provides ultra low leakage general purpose bidirectional I/O cells.
JPEG codec is designed to provide high performance solution for jpeg decoder and encoder.
64-bit RISC-V core with out-of-order pipeline based complex for Linux-based embedded systems
64-bit RISC-V core with out-of-order pipeline based complex.
64-bit RISC-V core with in-order dual issue pipeline based complex for Linux-based systems
64-bit RISC-V core with in-order dual issue pipeline based complex.
32-bit RISC-V core with in-order single issue pipeline for Linux-based systems
32-bit RISC-V core with in-order pipeline.
1.8V General Purpose I/O Inline Pad Set
The 1.8V GPIO library provides general purpose bidirectional I/O cells.
64-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ AX25MP 64-bit multicore CPU IP is based on AndeStar™ V5 architecture.
32-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture.
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
The BRIDGE_UART_I2C IP Core provides a simple and convenient way to interface a standard UART bus to a standard I2C bus.
Fast Fourier Transformation (FFT) calculation IP block.
The CryptoManager RT-6xx v3 Root of Trust family from Rambus is the latest generation of fully programmable FIPS 140-3 compliant …
Third-Generation, High-Performance CPU Based on DynamIQ Technology Built for powering next-generation 5G solutions Designed for d…
Single 512-bit SIMD DSP for Vision/Radar/Lidar/AI
Built on our latest Xtensa NX architecture and offers up to 2.18TOPS of performance The Cadence® Tensilica® Vision Q7 DSP deliver…
Library of mathematical and floating point (FP) components
Optimized for efficient hardware implementation, the Synopsys Foundation Cores include a library of mathematical and floating poi…
Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market
Customers are increasingly utilizing third-party standards-based IP in their designs, but face several challenges.
IP Solutions for the AMBA Interconnect
The Synopsys IP solutions for the ARM® AMBA® interconnect include synthesizable IP, verification IP (VIP) and automated assembly …
IP Prototyping Kits for USB, DDR, MIPI, PCI Express protocols
The Synopsys IP Prototyping Kits, part of the IP Accelerated initiative, center around a , out-of-the-box reference design that c…
As more functionality is integrated into an SoC, it is costly and time consuming to develop and maintain necessary functional blo…