Overview
The Synopsys IP Prototyping Kits, part of the IP Accelerated initiative, center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary system-on-chip (SoC) integration logic for a specific IP protocol, implemented on a Synopsys FPGA-based prototyping system.
With a proven reference design for the IP, designers can be instantly productive, enabling them to accelerate the integration of IP into their target SoC, optimize the IP configuration, and develop drivers and software applications with real world I/Os and hardware. The prototyping kit provides prototyping hardware with automation tools, and scripts and configuration files enabling fast iteration.
Learn more about PCI Express IP core
Madhumita Sanyal, Synopsys
Richard Solomon
This paper will begin with a quick overview of the specification and its application space, and then go into details such as bandwidth and clocking considerations, PHY interface differences, power management impacts, and the tradeoffs related to choices around link-layer changes. These changes may impact the transaction and application layers of devices moving from PCIe to M-PCIe, and the paper will detail those issues. A basic understanding of PCI Express concepts is helpful but not required.
This paper discusses the integration and system verification challenges encountered when integrating a PCI Express digital intellectual property (IP) core into a Gigabit Ethernet design
This article discusses the road to achieving compliance and the role that Synopsys DesignWare Intellectual Property (IP) for PCI Express can play in helping to achieve interoperability and compliance
This application note provides you with a very brief introduction to the emerging PCI Express protocol and explains how selecting the right digital and mixed signal IP can accelerate the implemention of this new standard into your designs.