Overview
The Synopsys IP solutions for the ARM® AMBA® interconnect include synthesizable IP, verification IP (VIP) and automated assembly with Synopsys’ coreAssembler tool. The Synopsys IP for the AMBA interconnect allows designers to rapidly integrate infrastructure components into their systems-on-chip (SoC)
and verify results with less risk and a reduced design cycle. Complementing the synthesizable IP is the VIP for AMBA interconnect, which includes the master, slave and monitor, providing designers with a quick and efficient way to verify AMBA interconnect-based SoCs. The Synopsys coreAssembler tool provides an automated method for assembling and configuring IP in a subsystem and develops an initial verification testbench for both the AMBA 2.0 and AMBA 3 AXI, AMBA 4
AXI and ACE-Lite protocol-based designs. This automation reduces the complexity of designing AMBA-based subsystems and improves overall productivity for faster time-to-results.
Learn more about Bus Fabric IP core
Leading portfolio of engineering solutions positions Synopsys to capitalize on the continued expansion of digital and physical AI and the AI-driven transformation of engineering.
The companies signed an expansive, multi-year agreement to jointly develop GPT-Synopsys, a specialized model, optimized to use Synopsys EDA tools to perform semiconductor design workflows.
The multi-year agreement marks the expansion of Synopsys' silicon IP business to serve increasing demand for application-optimized IP with Amazon as its lead customer.
Open and Secure Synopsys Autopilot Platform Accelerates Engineering Productivity, Improves Design Quality, and Achieves Faster Closure Across Silicon to Systems
New collaborations span A14 design enablement, AI-assisted engineering workflows, CoWoS® support for multi-die designs, and unified multiphysics signoff
Learn how AVSBus 2.0 VIP validates power delivery in AI and data center SoCs.