This core is a full implementation of the Triple DES encryption algorithm.
- Symmetric Crypto
- now
- Implemented according to th…
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
This core is a full implementation of the Triple DES encryption algorithm.
Serial Peripheral Interface - Master/Slave
The DSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signa…
Industry reference DVB-RCS turbo decoder
TC1000 implements the turbo code specified by DVB-RCS for Interactive 2-way satellite systems.
The W65C02S IP is a 8-bit 65xx Microprocessor available in GDSII Hardcore, RTL Softcore, and FPGA Specific Firm Cores.
The W65C02S IP is a 8/16-bit 65xx Microprocessor available in GDSII Hardcore, RTL Softcore, and FPGA Specific Firm Cores.
This TSMC 3nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm.
This TSMC 2nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 2nm.
Silicon Library (SLI) HDMI 2.0 RX IP solution, which consists of PHY analog IP and digital LINK IP, is compliant with HDMI 2.0b standard.
Silicon Library (SLI) HDMI 2.0 TX IP solution, which consists of analog PHY IP and digital LINK IP, is compliant with HDMI 2.0b standard.
Analog Switch with Gate Voltage Booster on TSMC 40nm
This Analog Switch IP contains 3 cells of Charge Pump, 500Ω Switch and 2kΩ Switch.
This OPAMP has rail-to-rail input and wide power supply voltage range on T40ULP ESF3.
Low Power Comparator on TSMC 40nm
This Comparator is low power supply voltage operation and low current consumption on T40ULP ESF3.
High-Speed Comparator on TSMC 40nm
This Comparator is high speed, wide supply voltage range operation on T40ULP ESF3.
Voltage Detector (3ch) on TSMC 40nm
This Voltage Detector is to check power supply level operating at lower power supply voltage and low current consumption on T40ULP ESF3.
Temperature Sensor (with analog output buffer) on TSMC 40nm
The Renesas Temperature Sensor IP including Analog Buffer outputs an analog voltage which corresponds to the detected temperature of LSI on TSMC 40nm
Temperature Sensor (with analog output buffer) on TSMC 28nm
The Renesas Temperature Sensor IP including Analog Buffer outputs an analog voltage which corresponds to the detected temperature of LSI on TSMC 28nm
Temperature Sensor (with analog output buffer) on TSMC 22nm
The Renesas Temperature Sensor IP including Analog Buffer outputs an analog voltage which corresponds to the detected temperature of LSI on TSMC 22nm
Temperature Sensor with ADC on TSMC 28nm
The Renesas Temperature Sensor IP including ADC outputs a digital code which corresponds to the detected temperature of LSI.
12bit 2MSps A/D Converter - TSMC T22ULP
This IP is Successive Approximation Register (SAR) Analog to Digital Converter TSMC 22nm
8 - 24MHz Xtal Oscillator on TSMC 22nm
This IP is Xtal Oscillator for MHz clock generation on TSMC 22nm