Voltage Detector (3ch) on TSMC 40nm
This Voltage Detector is to check power supply level operating at lower power supply voltage and low current consumption on T40ULP ESF3.
Overview
This Voltage Detector is to check power supply level operating at lower power supply voltage and low current consumption on T40ULP ESF3. The detection level can be selected from 1.52V to 3.72V at 45 steps. The detector has 2 modes, rise detection mode and fall detection mode.
Key features
- Voltage Detector 3ch
- 45 levels for VCC monitoring about 50mV steps
- Hysterisis function
- Available Detecting of VCC falling/ Detecting of VCC rising mode
- Output load =< 1 [pF]
Block Diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 40nm | LP | Available on request |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Voltage Monitor IP core
Renesas Develops 3nm TCAM Technology Combining High Memory Density and Low Power, Suitable for Automotive SoCs
Renesas Partners with Indian Government to Drive Innovation Through Startups and Industry-Academia Collaboration, Strengthening India’s Semiconductor Ecosystem
Renesas Completes Acquisition of Altium
Industry's First General-Purpose 32-bit RISC-V MCU Core Expands Design Freedom
Renesas Introduces Industry's First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core
Frequently asked questions about Voltage Monitor IP cores
What is Voltage Detector (3ch) on TSMC 40nm?
Voltage Detector (3ch) on TSMC 40nm is a Voltage Monitor IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc Available on request.
How should engineers evaluate this Voltage Monitor?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Voltage Monitor IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.