Radar processing IP suite for Advanced Driver Assistance Systems
The eSi-ADAS™ is a suite of radar accelerator IP including a Radar co-processor engine, they enhance the overall performance and …
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Radar processing IP suite for Advanced Driver Assistance Systems
The eSi-ADAS™ is a suite of radar accelerator IP including a Radar co-processor engine, they enhance the overall performance and …
Power Management Unit (2.3 - 3.0V output voltage, load current 150mA)
130iHP_PMU_02 is designed to form stabilized voltage with overcurrent indication (bit OVC).
Kalman Filter hardware accelerator
The eSi-Kalman core provides hardware acceleration for Kalman Filtering (KF) and related target tracking algorithms, such as meas…
High performance FFT optimised for Radar
A configurable efficient pipelined radix-2 squared FFT with additional functionality making it optimised for point cloud generati…
The eSi-SHA256 core is an easy to use SHA hash accelerator peripheral for both SHA256 and SHA224.
The eSi-SHA1 core is an easy to use SHA1 hash accelerator peripheral.
Combined ChaCha20 and Poly1305 core
The eSi-CHACHA20-POLY1305 core is an easy to use APB hardware accelerator peripheral that is fully compliant with the IETF RFC753…
CM6217co is a low-power general purpose Temperature Sensor IP featuring 12-bit parallel digital readout (2’s complement 8-bit int…
Ceva-SensPro is a family of DSP cores architected to combine vision, Radar, and AI processing in a single architecture.
Narrow band - IoT Release-14 e-NodeB Protocol Stack (L2-L3) Software IP
This NB-IoT eNodeB Protocol Stack IP supports significant and mandatory features specified by 3GPP Release 14 versions of NB-IoT …
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 28HPC
The capacity of the Display Port 1.4 Rx IP Channel is supported.
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE 4…
SD 5.1 / eMMC 5.1 Host Controller IP
Our Host IP is specially designed to combo both SD eMMC features.
1.8-3.6V to 2.7-3.0V step up DC/DC converter
130iHP_DCDC_01 is a high-performance step up DC/DC converter designed to operate with 1.8-3.6V input voltage.
Codasip Studio is a set of Electronic Design Automation (EDA) tools for processor design and customization.
Single-core video codec - HEVC, AVC
Single-core video codec - HEVC, AVC
Power Management Unit (2.3 - 3.0V output voltage, load current 20mA)
130iHP_PMU_01 is designed to form stabilized voltage with overcurrent indication (bit OVC).
130iHP_PA_03 is based on AB class power amplifier with a preamplifier.
Arasan Chip Systems, the provider of IP for Mobile Storage Standards, presents its latest xSPI Master IP for access to NOR Flash …
12-bit 1-channel 1 to 10 kSPS SAR ADC
130iHP_ADC_01 employs high-performance successive approximation architecture.