Arasan to demonstrate the industry's first MIPI SWI3S™ IP at the MIPI Member meet in Taipei
Arasan provides a Total SWI3S™ IP Solution including the SWI3S™ PHY which will be available on multiple foundry nodes 22nm and below.
Vendor:
Arasan Chip Systems Inc.
Category:
SPI / QSPI XSPI
xSPI Master IP | NOR IP
Arasan Chip Systems, the provider of IP for Mobile Storage Standards, presents its latest xSPI Master IP for access to NOR Flash …
Overview
Arasan Chip Systems, the leading provider of IP for Mobile Storage Standards, presents its latest xSPI Master IP for access to NOR Flash Devices. This Universal NOR Flash IP supports a variety of NOR Devices and multiple Protocols, combines ease of use with high reliability, low power and speed under all conditions, including automotive applications.
The xSPI master IP supports the xSPI JESD251 standard from a standard AXI4 slave interface, and also features backwards compatibility support for Octal SPI, QSPI, DSPI, and SPI interfaces. Also supports JEDEC SFDP Standard. It is designed so that a user design may immediately access memory from the xSPI device in SPI mode, or alternatively issue a command to switch to any other mode. Additionally, a DMA command may be issued to copy memory from the xSPI device to anywhere else on the bus.
The xSPI master IP supports the xSPI JESD251 standard from a standard AXI4 slave interface, and also features backwards compatibility support for Octal SPI, QSPI, DSPI, and SPI interfaces. Also supports JEDEC SFDP Standard. It is designed so that a user design may immediately access memory from the xSPI device in SPI mode, or alternatively issue a command to switch to any other mode. Additionally, a DMA command may be issued to copy memory from the xSPI device to anywhere else on the bus.
Key features
- JESD 251 compliant
- Protocols 1 & 2
- JEDEC SFDP Compliant
- 8b and 4b xSPI
- Octal SPI, QSPI, DSPI
- Resets into SPI mode
- 24 or 32b addressing
- User selectable cmds
- XIP high speed support
- AXI4 Execute in Place
- Parameterized width
- Full & Narrow burst
- Max Bus Throughput
- AXI4 DMA Host
- High speed bulk operations
- Parameterized width
- Full & Narrow burst
- Max bus throughput
- Read Straight to RAM
- AXI4-Lite Configuration Port
- Low level command access
- JESD SFDP support
- High level software library
Block Diagram
SUREBOOT™ xSPI Master IP | NOR IP block diagram
Benefits
- Arasan xSPI Host IP is an Universal SPI Controller supporting Octal SPI, QSPI, DSPI & SPI to access NOR Flash Devices.
- Total xSPI IP Solution includes xSPI Device, HDK & SW
- Low Gate Count & Low Power
What’s Included?
- Verilog RTL Code
- Homogenous Verilog Test Environment
- Optional UVM Test Environment
- Synthesys Scripts
- xSPI Emulator suitable for integration testing
- Software Configuration Library
- User Guide
- Software configuration library
Specifications
Identity
Part Number
SUREBOOT™ xSPI Master IP | NOR IP
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP
Videos
Arasan JEDEC compliant xSPI IP a superset of our Octal SPI, QSPI, SPI and PSRAM IP
Arasan Chip Systems, a leading provider of IP for Mobile Storage Standards, presents its JEDEC JESD251C Compliant xSPI IP, a superset of its Octal SPI IP, QSPI IP and PSRAM IP in addition to xSPI providing access to any NOR Flash Device. Arasan's Total xSPI IP, which includes the xSPI PHY IP combines ease of use with high reliability, low power and speed under all conditions, including automotive applications.
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about SPI / QSPI / xSPI IP cores
What is xSPI Master IP | NOR IP?
xSPI Master IP | NOR IP is a SPI / QSPI XSPI IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.
How should engineers evaluate this SPI / QSPI XSPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.