SMIC 55nm LL LPDDR interface for DRAM application
SMIC
•
HQ:
China
IP
- Controller
- SMIC
- 55nm
- LL
- Silicon Proven
Compare 288 LPDDR IP Listing from 31 vendors
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IP
- Controller
- SMIC
- 65nm
- LL
- In Production
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SMIC 65nm LL LPDDR interface for mobile-DDR application
SMIC• HQ: ChinaIP
- Controller
- SMIC
- 65nm
- LL
- In Production
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IP
- Controller
- SMIC
- 55nm
- LL
- In Production
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Chipus Microelectronics• HQ: Brazil
The DDR PHY is designed to support LPDDR4, LPDDR4x and LPDDR5 SDRAM.
- Controller + PHY + 1
- LPDDR4
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Truechip Solutions• HQ: USA
The LPDDR4X Verification IP provides an effective & efficient way to verify the components interfacing with the LPDDR4X interface…
- Verification IP
- Controller
- LPDDR4
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Synopsys, Inc.• HQ: USA
The DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3, DDR3L (1.3…
- Controller + PHY + 1
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LPDDR5T / LPDDR5X / LPDDR5 Controller
Rambus, Inc.• HQ: USAThe LPDDR5 Controller supporting LPDDR5T, LPDDR5X, LPDDR5 controller core is designed for use in applications requiring high memo…
- Controller
- LPDDR5 + 1
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Rambus, Inc.• HQ: USA
The LPDDR4X/4 controller core is designed for use in applications requiring high memory throughput at low power including mobile,…
- Controller
- LPDDR4
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LPDDR4X/4 & LPDDR5T/5X/5 Combo Controller
Rambus, Inc.• HQ: USAThe LPDDR4 and LPDDR5 combo controller core is designed for use in applications requiring high memory throughput at low power inc…
- Controller
- LPDDR4 + 1
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OPENEDGES Technology, Inc.• HQ: Korea
Features a mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and low-power environm…
- PHY
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DO-254 DDR Memory Controller 1.00a
Logicircuit, Inc.• HQ: USAA dedicated embedded block multi-port memory controller that greatly simplifies the task of interfacing Spartan-6 devices to the …
- Controller
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ZeroPoint Technologies AB• HQ: Sweden
Purpose-built AI model compression IP, combining software compression with hardware decompression for static model data and hardw…
- Data Compression
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Cadence Design Systems, Inc.• HQ: USA
The Gold Standard Memory Model is intended to be compatible with the anticipated JEDEC LPDDR6 standard for your IP, Subsystem, So…
- Verification IP
- Controller
- LPDDR6
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1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
Certus Semiconductor• HQ: United StatesA TSMC 22nm Inline, Flip Chip compatible library with GPIO, ODIO, HDMI, LVDS, & Analog Cells.
- TSMC
- 22nm
- ULL
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1.8V/3.3V Multi-Voltage GPIO in TSMC 28nm
Certus Semiconductor• HQ: United StatesA Fail-Safe Digital I/O Library.
- TSMC
- 28nm
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Three-Speed Inline Library with Open Drain I/0 in TSMC 22nm
Certus Semiconductor• HQ: United StatesA TSMC 22nm Inline, Flip Chip compatible library with three-speed GPIOs and I2C compliant ODIO.
- TSMC
- 22nm
- ULL
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1.8V/3.3V Switchable GPIO in TSMC 28nm
Certus Semiconductor• HQ: United StatesA TSMC 28nm Wirebond I/O Library with a switchable 1.8V/3.3V GPIO, with Specialized RF Wirebond Cells for LNAs.
- TSMC
- 28nm
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InPsy• HQ: Taiwan (R.O.C.)
Our I/O Library, meticulously crafted to support a wide range of interfaces critical for modern electronic designs.
- GPIO
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High Performance AES-XTS/ECB Core
Synopsys, Inc.• HQ: USAWith the tremendous data and bandwidth growth in our connected world, security is essential to protect private and sensitive data…
- AES