DDR PHY

Features a state-of-the-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and low-power environments. This architecture enables OPHYs to overcome issues with long-term impedance drift and clock phase drift, enabling impedance and clock phase updates without interrupting data traffic. Programmable timing at OPHY boundary combines flexibility with analog precision, resulting in low read/write latency between OPENEDGES Memory Controller (OMC) and the DRAM.

OPHYs are designed with subsystem and system-level considerations in mind. Built-in power management logic and advanced PLL design allow aggressive power state management and optimal system power usage. Tight integration with OPENEDGES Memory Subsystem enables ActiveQoS bandwidth and latency control for maximum performance of the SoC memory subsystem. At the system level, OPHYs have been designed to minimize package substrate layer and PCB layer requirements, enabling usage in cost-sensitive applications.

OPENEDGES DDR PHY Availability

LPDDR6/5X PHY

Available process nodes:4nm

LPDDR5/4X/4 PHY

Available process nodes: 14nm

LPDDR4X/4 PHY

Available process nodes: 12nm, 14nm, 16nm

LPDDR3/DDR3 PHY

Available process nodes: 28nm

DDR5

Available process nodes: 5nm

LPDDR5X/5/4X/4 PHY 

Available process nodes: 5nm, 7/6nm, 12nm, 16nm 

LPDDR5/4 PHY

Available process nodes: 5nm, 8nm

LPDDR/4 PHY

Available process nodes: 22nm

LPDDR4/3/ DDR4/3 PHY

Available process nodes:28nm

Compliant with PHY standards

• JEDEC compliant LPDDR6/5X/5/4X/4, DDR5 support
• DFI Interface Compliant

Flexible Configuration

• LPDDR6 : 24-/48-bit data width per channel
• LPDDR5x/5/4: 16-/32-bit data width per channel
• Supports multiple DFICLK: CK: WCK ratio
• Multiple DFICLK: CK: WCK ratios
• Up to 4 ranks with Tx and Rx channel equalization

Maximum Data Rates

• Up to 14400 Mbps for LPDDR6 (Planning)
• Up to 8533 Mbps for LPDDR5x
• Up to 4266 Mbps for LPDDR4x

Programmable State Machine (PSM)

• Proprietary microcontroller and custom ISA enable customizable DFT features and multiple LPDDR standard support efficiently while reducing the area

Multiple FSPs and the LP States

• Supports up to 4 frequency set points (FSPs)
• Supports multiple low power states for system power optimization

Workload-Driven Performance Optimization​

• Intuitive visualization and analysis of memory subsystem architecture and performance
• Workload-driven memory subsystem architecture and QoS optimization

Configurability with Flexible Applications

• Configurable channel and floor-plan allow connection to different DRAM package types and lane ordering
• Minimal package substrate/PCB layer requirements enables PHY usage in low-cost applications

​Performance

• PSM enables accelerated firmware-based training
• Ultra-fast fractional training
• Programmable PHY boundary timing provides low read/write latency
• Fast switching between FSPs

​Capacity

• Channel equalization and fast timing adjustment circuits enable 4 rank support to maximize capacity

​Power

• Power-saving modes with a variety of exit times
• Multiple voltage domains to optimize voltage versus frequency

Hard & Soft IP

• GDSII, LEF, LVS, timing models, etc
• Verilog behavior models and encrypted RTL
• Synthesis and STA constraints
• Example test benches

Documentation

• PHY Technical Reference Manual
• Implementation, Package, and PCB design guidelines