Learn more about LPDDR IP core
JEDEC has just released the LPDDR6 specification that is expected to take the LPDDR DRAM market to new heights with data transfer speeds that can reach up to 14.4Gbps, which is a 50% improvement over LPDDR5X speeds. LPDDR6 device density can range from 4 GB to 64 GB.
This solution brief highlights how Samsung’s mainstream 8nm process node and LPDDR5X (LP5X) memory together deliver an optimized balance of performance, bandwidth, power efficiency, and cost. The combination enables scalable AI inference across diverse computing environments, from edge devices and AI appliances to emerging inference-focused AI infrastructure, making advanced AI deployment more accessible for startups, fabless innovators, and OEMs alike.
Next-generation automotive systems are advancing beyond the limits of currently available technologies. The addition of advanced driver assistance systems (ADAS) and other advanced features requires greater processing power and increased connectivity throughout the vehicle.
Cadence leads the market with its DDR5 MRDIMM 12.8 Gbps Gen2, TSMC N3P IP system solution, establishing a new benchmark for industry-leading PPA. Key industry leaders have already adopted this solution, which is now also available in the TSMC N2P and N5/N4P process nodes.
Understand memory-aware ASIC design for AI workloads, from memory hierarchy and dataflow to NoC, DMA, and hardware-software co-design.
