5G IP Listing

5GHz RF Buffer, Vdd=800mV, Idd=6mA

• GlobalFoundries
• 22nm
• FDX
• Pre-Silicon

Analog-PLL For Frequency Multiplying on TSMC 28nm HPM/HPC

• TSMC
• 28nm
• HPC +1
• Available on request

5GHz SSCG with 25MHz reference clock, UMC 0.11um 20T HS/FSG Logic process.

• UMC
• 110nm
• HS

5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.

• UMC
• 110nm
• HS

5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.

• UMC
• 110nm
• HS

PSI5GLP_T4 is a low jitter PLL operating from 3GHz to 5GHz continuously, and with the output divider it can cover 1/2 and 1/4 spe…

• TSMC
• 40nm
• G

USB 5G,10G, 20G and 4.0 Device router controller is a configurable core and implements the USB device functionality and can be in…

• USB
• Silicon Proven, Certified, FPGA validated, Interop Tested
• Now
• USB 5G,10G, 20G

The ODT-ADS-12B5G-T28 is an ultra-highperformance time-interleaved ADC designed in a 28nm CMOS process.

• TSMC
• 28nm

The USB Super-Speed+ PHY IP is a compact and power-efficient interface solution that fully supports the USB 3.2 Gen1 and Gen2 spe…

• Single-Protocol PHY

Leveraging the benefits of USB 10Gbps and 5Gbps device controller, USB 20Gbps is designed using the FPGA built-in transceiver.

• USB
• Now

To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to de…

• UniPro

With sophisticated architecture and technology, the USB3.1 transceiver IP with PMA and PCS layer is designed for low power and hi…

• Single-Protocol PHY

The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum.

• USB 3.2

The PCIe2 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into PCI …

• Single-Protocol PHY
• Silicon Proven; Design Ready(SMIC,28)
• Immediate

This USB3.0 PHY IP is designed according to USB3.0 and USB2.0 specification.

• Single-Protocol PHY
• Silicon proven

The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum.

• USB 3.2
• TSMC
• 3nm
• N3E

Granite Semicom has just shipped GDS-II of its totally-integrated (no off-chip components) Clock-Driver and Clock-Multiplying-Uni…

• TSMC
• 40nm
• LP

Granite SemicCom's Digital PLL is intended for applications such the Clock-Multiplying-Unit in a SERDES or a Clock-Driver with fr…

• TSMC
• 40nm
• G

The CL12812M8RIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DS…

• TSMC
• 12nm
• FFC
• Silicon Proven

Full compatible with PIPE4.2 interface specification

• SMIC
• 14nm
• SF+