Universal G704-E1 Framer / Deframer Core
The iniG704-E1 framer core is designed to handle synchronous frame structures (Recommondation G.704) running on E1 carrier.
- TDM Framer
- Proven in ASIC and FPGA Technologies
- now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Universal G704-E1 Framer / Deframer Core
The iniG704-E1 framer core is designed to handle synchronous frame structures (Recommondation G.704) running on E1 carrier.
High-Level Data Link Controller
Inicore's iniHDLC family of High-Level Data Link Controller (HDLC) cores consist of a Receiver (FPR: From Primary Rate) and a Tra…
6809 compatible 8-bit microprocessor
iniCPU, a 8-bit micro processor, enables embedded computing and controlling on chip.
This core is a full implementation of the Triple DES encryption algorithm.
Serial Peripheral Interface - Master/Slave
The DSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signa…
Industry reference DVB-RCS turbo decoder
TC1000 implements the turbo code specified by DVB-RCS for Interactive 2-way satellite systems.
The W65C02S IP is a 8-bit 65xx Microprocessor available in GDSII Hardcore, RTL Softcore, and FPGA Specific Firm Cores.
The W65C02S IP is a 8/16-bit 65xx Microprocessor available in GDSII Hardcore, RTL Softcore, and FPGA Specific Firm Cores.
Graphics, compute and AI all on one processor, with one software stack
FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
AI-enhanced automation for smarter multi-die SoC and chiplet designs.
Ncore Multi-Die Interconnect IP
High-bandwidth, low-latency network-on-chip (NoC) interconnect for rapid modular innovation.
CryptoManager Root of Trust for Use with the Caliptra Specification
Root of Trust and Security Orchestration for Caliptra-based SoCs
Meets the requirements of 10,000-scale XPU clusters and high performance storage
High Performance, Small Area, Low Power | Flexible Controller Configuration Solution
Supports full protocol coverage from USB 2.0 to USB 3.2 Certified by USB-IF
This TSMC 3nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm.
This TSMC 2nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 2nm.
Silicon Library (SLI) HDMI 2.0 RX IP solution, which consists of PHY analog IP and digital LINK IP, is compliant with HDMI 2.0b standard.
Silicon Library (SLI) HDMI 2.0 TX IP solution, which consists of analog PHY IP and digital LINK IP, is compliant with HDMI 2.0b standard.
Analog Switch with Gate Voltage Booster on TSMC 40nm
This Analog Switch IP contains 3 cells of Charge Pump, 500Ω Switch and 2kΩ Switch.