Silvaco focuses on enabling the next generation of AI/ML, Cloud/Datacenter, Automotive and Autonomous Driving, IoT and 5G designs through a comprehensive offering of Silicon proven IP. Our portfolio includes a complete catalog of Interface IP, Amba Peripherals, Subsystems, MIPI IP and Automotive Communication Controller IP. Our experienced ASIC and Embedded Software designers have a rich history of designing SOCs with embedded microprocessors which are crucial to building small connected smart chips.
Ultra High-Speed Cache Memory Compiler - 2-Port Register File - TSMC N3P
The Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an cache …
AHB Secure Subsystem - ARM Cortex M3
The Secure AHB Performance Subsystem is a high-performance AHB subsystem that allows for a high level of hardware and software se…
AHB Performance Subsystem - ARM Cortex M0
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs n…
AHB Performance Subsystem - ARM Cortex M3
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs n…
AHB Low Power Subsystem - ARM Cortex M0
The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SO…
APB I2C Master/Slave Controller
The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS.
AXI Performance Subsystem - ARM Cortex A
The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needin…
Standard Cell Libraries GF 55nm
The Standard Cell libraries deliver thousands of optimized cells with each one being optimized for power, area, speed, routing, a…
The I3C Controller Lite is a configurable I3C controller that can be used in microcontroller-based environments to provide I3C co…
The I3C Target is a configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivity to…
The I3C Autonomous Target is intended for simple, data acquisition types of applications where a microprocessor is not needed to …
The I3C Controller is a configurable I3C controller that can be used in microcontroller-based environments to provide I3C connect…
Standard Cell Library, Low Voltage Operation 0.45 V TSMC N3P
The low voltage Standard Cell Library for the TSMC N3P process represents a breakthrough in power efficiency for high performance…
Bandgap Voltage Reference, 0.45 V Output, Low PPM/°C, TSMC N3P
Bandgap Voltage Reference, 0.45 V Output The Bandgap Voltage Reference IP is a 1.0 V input, low PPM/°C, 0.45 V reference voltage …
LDO Voltage Regulator, 250 mA, TSMC N3P
LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output The LDO IP is a 1.2V low-quiescent-current adjustable output vol…
LDO Voltage Regulator, Adjustable 0.45 V to 0.9 V Output, 30 mA, TSMC N3P
LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output The LDO IP is a 1.2V low-quiescent-current adjustable output volt…
The DTS Adapter from Silvaco enables an existing IEEE 1149.1 debug test system (DTS) to take advantage of the debug/test capabili…
APB to AHB-Lite Asynchronous Bridge
The APB to AHB-Lite Asynchronous Bridge translates an APB bus transaction (read or write) on one clock domain to an AHB Lite bus …
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction.
The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the si…