The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs n…
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional performance. This AHB Multi-matrix system contains a flexible Power Management Unit for controlling power sequencing of the CPU and peripherals. The PMU can easily be extended to control additional cores, peripherals and even analog subsystems on the same SOC.
Additionally, the subsystem includes two DMA controllers for easily moving data from user peripherals to internal SRAM.
Most of the supported CPUs are powerful enough to handle applications such as spectral analysis, FFT, and data manipulation, thus making the subsystem a good choice for IoT devices where computation has to be done at the edge.
The AHB Performance Subsystem includes a standard set of peripherals and cores that supports RTOS and software kernels. Included is a QSPI, serial flash controller for boot loading program images or operating as an Execute in Place (XIP) engine using non-volatile external flash memory with low power.
The AHB Performance Subsystem is soft IP that can be used in all the popular semiconductor technology nodes.
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AHB Performance Subsystem - ARM Cortex M0 is a CPU IP core from Silvaco, Inc. listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.