DDR3 and DDR4 Controller and PHY on TSMC 12nm
This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophi…
- Controller + 2
- DDR3 + 1
- TSMC
- 12nm
- FFC
- Available on request
Key ASIC was incorporated in the year 2005. In 2006, we were awarded Multimedia Super Corridor (MSC) Status by the Malaysia Digital Economy Corporation (MDEC). We started with the design of IP, ASIC, and SoC. In 2009, we were listed on the main board of KLSE. Khazanah and CIMB are our main investors.
Key ASIC is not only a leading ASIC / SoC design service company, we are also a turnkey service company from spec-in to system module that focuses on AI chips, IoT, and medical applications. We are committed to providing customers with competitive SoC professional one-stop design services in terms of PPA (Performance, Power, and Area).
Based in Kuala Lumpur, Malaysia with R&D Centers in Malaysia and Tai Yuen Hi-Tech Industrial Park Taiwan, Key ASIC provides ODM and OEM of ASIC design services from Specification, RTL, Netlist to silicon, as well as process migration from GDSII.
Our experienced SoC designer and engineers combined with extensive manufacturing, logistics resources, and a flexible engagement model can provide Key ASIC customers with a comprehensive support system for modular ASIC innovation from IP development through prototype to production.
DDR3 and DDR4 Controller and PHY on TSMC 12nm
This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophi…
As the demand for higher data rates and increased serial I/O density intensifies, the performance requirements for next-generatio…
KA13UGUSB20ST001 is USB2.0 physical layer transceiver (PHY) integrated circuits.
LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
KA16UGLVDS01ST001 is a LVDS IO handling data rate up to 50Mbps with a maximum loading of 60pF.
USB 2.0 On-chip oscillator, termination resistors, and DP/DM short circuit protection (0.18u)
The KA18USB20 consists of the digital and analog blocks of the USB Transceiver Macrocell (UTMI) specifications.
The KA13ETHB33 is a single-port PHY with an MII (Media Independent Interface).
The inline CUP I/O library provide 3.3V bi- directional I/O cells with pull -up, pull-down features, Schmitt trigger and a range …
PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
KA13UGPEP20ST001 provides a PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application.