Vendor: Key ASIC Category: Single-Protocol PHY

PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface

KA13UGPEP20ST001 provides a PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application.

Overview

KA13UGPEP20ST001 provides a complete PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application. It has a serial interface and PIPE3 compliant digital interface.
KA13UGPEP20ST001 offers a modular architecture, diagnostic access, and testability support, in addition to low power and small area.

Key features

  • Support for 2.5Gbps/5.0Gbps data rate for PCIe1.1 and PCIe2.0
  • Support Loop-back BERT and Loop-back
  • Support Self-calibration for On-die-termination
  • Industry standard PIPE2
  • Full power management support
  • Power saving modes support
  • Support low-power transmitter
  • Beacon transmit and detect
  • Receiver detection
  • Built-in 8B/10B encoding/decoding
  • 16 bit data interface
  • Single channel clock & data recovery, serial data transmit and serializer-deserializer
  • Built-in self test
  • Extensive test and diagnostic access modes

Benefits

  • Support for 2.5Gbps/5.0Gbps data rate for PCIe1.1 and PCIe2.0, Loop-back BERT and Loop-back, and Self-calibration for On-die-termination

Specifications

Identity

Part Number
KA13UGPEP20ST001
Vendor
Key ASIC
Type
Silicon IP

Provider

HQ: Malaysia

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Frequently asked questions about Single-Protocol PHY IP

What is PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface?

PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface is a Single-Protocol PHY IP core from Key ASIC listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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