Vendor: Digital Blocks, Inc. Category: Ethernet

RTP/UDP/IP Protocol Hardware Stack – H.264/H.265 NAL Video Streams Packet Processing

The DB-RTP-UDP-IP-NAL Intellectual Property Core is an RTP/UDP/IP Protocol Hardware Stack with the following protocol processing …

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Overview

The DB-RTP-UDP-IP-NAL Intellectual Property Core is an RTP/UDP/IP Protocol Hardware Stack with the following protocol processing units:

  •  RTP Packet Processor
  •  UDP Packet Processor
  •  IP Packet Processor
  •  MAC Frame Layer Processor

The image below  depicts the RTP/UDP/IP Protocol Hardware Stack SoC IP Core embedded within an FPGA/ASSP/ASIC device.

For RX (i.e., receiving packets from the network), there is optional packet reordering to absorb network jitter.

For both TX/RX, multiple NAL video streams supported. The DB-RTP-UDP-IP-NAL targets H.264 NAL Streams. See DB-RTP-UDP-IP-AV for raw, uncompressed RGB/YUV video streams.

Key features

  • RTP/UDP/IP Protocol Hardware Stack, targets H.264 NAL Streams. See DB RTP-UDP-IP-AV for raw, uncompressed RGB/YUV video streams 
  • Internet Protocol (IP) Packet Processor:  
    • IPv4 and IPv6 (optional) & ICMP (Internet Control Message Protocol) Protocol 
    • IP header checksum generator (transmitter) & check (receiver), user selectable Maximum Transmission Unit (MTU), Unicast, Broadcast &  Multicast Packet support 
    • Compliance with IETF IPv4/IPv6 RFCs 
  • User Datagram Protocol (UDP) Packet Processor: 
    • UDP header checksum generator (transmitter) & check (receiver) – programmable on/off 
    • Compliance with IETF UDP RFCs 
  • Real Time Transport Protocol (RTP) Packet Processor 
    • Multiple TX/RX NAL streams supported 
    • For RX, optional Packet reordering to absorb network jitter 
    • Compliance with IETF RTP RFCs 
  • Address Resolution Protocol (ARP) Packet Processor (client/server) with 4-16 entry ARP cache 
  • High Speed Data Interface to user Host Application (typical clock rates): 
    • 10/100/1000 MbE: 32-bit @ 2.5/25/125 MHz, AXI4-Stream or Avalon-ST 
    • Contact Digital Blocks regarding 10 GbE higher network requirements 
  • Host set-up & control via Control & Status Registers and Interrupt Controller 
    • 32-bit @ user clock rate AXI4-Lite or Avalon-MM  
    • Optional hardwired no-register setup 
  • Pipeline, High Clock Rate, Low Latency architecture & design 
  • Fully synchronous, synthesizable RTL Verilog SoC IP core 
     

Block Diagram

DB-RTP-UDP-IP-NAL block diagram

What’s Included?

  • Verilog RTL Source or technology-specific netlist.
  • Comprehensive testbench suite with expected results.
  • Synthesis scripts.
  • Installation & Implementation Guide.
  • Technical Reference Manual.

Specifications

Identity

Part Number
DB-RTP-UDP-IP-NAL
Vendor
Digital Blocks, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Digital Blocks, Inc.

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What is RTP/UDP/IP Protocol Hardware Stack – H.264/H.265 NAL Video Streams Packet Processing?

RTP/UDP/IP Protocol Hardware Stack – H.264/H.265 NAL Video Streams Packet Processing is a Ethernet IP core from Digital Blocks, Inc. listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

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