System controller IP cores provide centralized control and coordination of system operations in modern SoC and ASIC designs, ensuring efficient management of subsystems and resources.
These IP cores handle functions such as power management coordination, clock and reset control, boot sequencing, and system monitoring, acting as the control hub of the chip.
This catalog allows you to compare system controller IP cores from leading vendors based on control capabilities, integration flexibility, latency, and process node compatibility.
Whether you are designing embedded systems, automotive platforms, industrial controllers, or complex multi-domain SoCs, you can find the right system controller IP for your architecture.
Partial Reconfiguration AXI Shutdown Manager IP
The Partial Reconfiguration (PR) AXI Shutdown Manager can be used to make the AXI interfaces between a Reconfigurable Partition a…
Platform Manager Utility Function Core IP
Platform Management Core IP adds two key power-management functions to Platform Manager: Fault Logging and Enhanced Closed-loop T…
The LogiCORE™ IP System Management Wizard provides a solution for system-monitoring Xilinx UltraScale™ architecture-based devises.
Partial Reconfiguration Decoupler IP
The Partial Reconfiguration (PR) Decoupler IP provides logical isolation capabilities for PR designs.
Partial Reconfiguration Controller
The Partial Reconfiguration Controller (PRC) IP provides management functions for Partial Reconfiguration designs.
Mutex provides a mechanism for mutual exclusion to enable one process to gain exclusive access to a particular resource in a mult…
Mailbox features a bi-directional communication channel between two processors.
AXI SystemACE Interface Controller
The AXI System ACE™ Interface Controller (AXI SYSACE) is the interface between the AMBA® AXI4 Lite and the Microprocessor Unit (M…
The AXI Hardware ICAP enables an embedded microprocessor, such as MicroBlaze, to read and write the FPGA configuration memory thr…
AXI External Peripheral Controller
The AXI External Peripheral Controller (AXI EPC IP Core) supports data transfers between the AXI4 Interface and external synchron…
The XPS PS2 Controller is a PLB (Processor Local Bus) slave that is designed to control PS2 devices such as keyboard and mouse.
In a multi processor environment the processors share common resources.
XPS Mailbox features a bi-directional communication channel between two processors.
The XPS HWICAP (Hardware ICAP) IP enables an embedded microprocessor, such as the MicroBlaze™ or PowerPC™ to read and write the F…
XPS External Peripheral Controller
This specification defines the architecture and interface requirements for the External Peripheral Controller (EPC).
The XPS BRAM Interface Controller is a Xilinx IP module that incorporates a PLB V4.6 (Processor Local Bus) interface.
Peripheral Interface Adapter (PIA)
The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member.
The Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller is a module that attaches to one LMB.
The system controller core connects the system CPU to system memory, PCI bus, IO ports and external communication links.
Intel™ 8279 Programmable Keyboard/Display Interface Device
The AL8279 core is the VHDL model of the Intel™ 8279 Programmable Keyboard/Display Interface device designed for use with Intel m…