Vendor: Xilinx, Inc. Category: System Controller

LMB BRAM Interface Controller

The Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller is a module that attaches to one LMB.

Overview

The Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller is a module that attaches to one LMB. It supports the LMB bus protocol and byte enable architecture. Any access size up to the width of the LMB data bus is permitted. The LMB BRAM Interface Controller is the interface between the LMB and the BRAM block peripheral. A BRAM memory sybsystem consists of the controller along with the actual BRAM components that are included in the BRAM block peripheral.

Key features

  • LMB v1.0 bus interfaces with byte enable support
  • Used in conjunction with BRAM block peripheral to provide fast BRAM memory solution for MicroBlaze™ ILMB and DLMB ports
  • Supports byte, half-word, and word transfers
  • Supports optional BRAM error correction and detection
  • Supports multiple LMB masters
  • Support for extended address up to 64 bits

Specifications

Identity

Part Number
LMB BRAM Interface Controller
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

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Frequently asked questions about system controller IP cores

What is LMB BRAM Interface Controller?

LMB BRAM Interface Controller is a System Controller IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this System Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this System Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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