Vendor: Cadence Design Systems, Inc. Category: PMBus

Simulation VIP for PMBus

Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for PMBus provides a bus functional model (BFM), in…

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Overview

Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for PMBus provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. The VIP for PMBus is designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, and helps to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for PMBus runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: PMBus v1.3.1 - Power System Management Protocol Specification Part I – General Requirements, Transport And Electrical Interface and Power System Management Protocol Specification Part II – Command Language.

Key features

  • MBus Devices
    • Controller, target, or host
  • Packet Error Checking
    • Performs PEC on transmit and receive data on applicable packets
  • Address Resolution Protocol
    • Resolve addresses for devices on the bus
  • Device Timeout
    • Device timeout condition detection
  • Command Protocol
    • All (Group, Extended, Zone read/write, Host Notify) command protocols with and without a packet error code
  • Clock Generation and Data Arbitration
    • Clock generation using defined clock timings and data arbitration
  • Clock Synchronization Between Two Managers
    • Clock synchronization when more than one manager drives the clock

Block Diagram

Simulation VIP for PMBus block diagram

Specifications

Identity

Part Number
Simulation VIP for PMBus
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

Learn more about PMBus IP core

VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems

This paper presents VolTune, an open-source runtime voltage control architecture that enables runtime tuning of FPGA supply voltages through FPGA-integrated control logic that abstracts low-level PMBus operations. VolTune provides both hardware-based and software-based control paths, allowing designers to balance deterministic low-latency operation against programmability.

Frequently asked questions about PMBus IP cores

What is Simulation VIP for PMBus?

Simulation VIP for PMBus is a PMBus IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this PMBus?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PMBus IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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