PMBUS Assertion IP

PMBUS Assertion IP provides an efficient and smart way to verify the PMBUS designs quickly without a testbench. The SmartDV's PMBUS Assertion IP is fully compliant with standard PMBUS Specification.

PMBUS Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

PMBUS Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Specification Compliance
• Supports all the PMBus commands as per the specs.
• Supports all the extended and normal command codes.
• Send byte command
• Receive byte command
• Write byte command
• Write word command
• Read byte command
• Read word command
• Process call command
• Block write command
• Block read command
• Group command
• Block write and read process call command
• Extended command read byte
• Extended command read word
• Extended command write byte
• Extended command write word
• Supports programmable clock frequency of operation.
• Bus-accurate timing.
• Packet Error Checking (PEC) support
• PEC Error.
• NACK for PEC code by slave.
• ACK for PEC code by master.
• Master asserted stop condition before PEC byte.
• NACK for command code byte by slave.
• NACK for second address byte after repeated start to same slaves.
• Implements all registers and commands as per the PMBUS specification.
• Assertion IP features
• Assertion IP includes:
• System Verilog assertions
• System Verilog assumptions
• System Verilog cover properties
• Synthesizable Verilog Auxiliary code
• Support Master mode, Slave mode, Monitor mode and Constraint mode.
• Supports Simulation mode (stimulus from SmartDV PMBUS VIP) and Formal mode (stimulus from Formal tool).
• Rich set of parameters to configure PMBUS Assertion IP functionality.

• Runs in every major formal and simulation environment.

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.