Vendor: SmartDV Technologies Category: PMBus

IPMB Verification IP

IPMB Verification IP provides an smart way to verify the IPMB two-wire bus.

Contact Provider Request Datasheet
Verification IP View all specifications

Overview

IPMB Verification IP provides an smart way to verify the IPMB two-wire bus. The SmartDV's IPMB Verification IP is fully compliant with version 1.0 and provides the following features.

IPMB Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

IPMB Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports IPMB specifications version 1.0.
  • Supports IPMB device types: Master, Slave.
  • Start and stop for all possible transfers.
  • Supports 7bit configurable Slave address.
  • Supports broadcast message capability.
  • Supports ACK/NACK mechanism.
  • Supports below network function mechanisms.
    • Chassis request/response
    • Bridge request/response
    • Sensor event request/response
    • Application request/response
    • Firmware request/response
    • Storage request/response
    • OEM request/response
  • Supports message transaction formats.
    • IPMB node-to-node transactions.
  • Supports out-of-Band access.
  • Supports non-intelligent i2c devices.
  • By using out-of-band access.
    • Host ACK followed by device payload.
    • Host NACK followed by STOP.
  • Built-in monitors for protocol checking, including a global bus monitor.
  • Functional coverage to cover all functionality of IPMB Slave and Master.
  • Callbacks in Master and Slave for various events.
  • Status counters for various events in bus.
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • IPMB Verification IP comes with complete test suite to test every feature of IPMB specification.

Benefits

  • Faster testbench development and more complete verification of IPMB designs.
  • Easy to use command interface simplifies testbench control and configuration of Master and Slave.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the IPMB testcases to certify IPMB Master/Slave device.
  • Examples showing how to connect various components, and usage of Master, Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
IPMB VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about PMBus IP core

VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems

This paper presents VolTune, an open-source runtime voltage control architecture that enables runtime tuning of FPGA supply voltages through FPGA-integrated control logic that abstracts low-level PMBus operations. VolTune provides both hardware-based and software-based control paths, allowing designers to balance deterministic low-latency operation against programmability.

Frequently asked questions about PMBus IP cores

What is IPMB Verification IP?

IPMB Verification IP is a PMBus IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this PMBus?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PMBus IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP