PMBus Synthesizable Transactor

PMBus Synthesizable Transactor provides an smart way to verify the PMBus component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's PMBus Synthesizable Transactor is fully compliant with standard PMBus 1.3.1 Specification and provides the following features.

• Fully compatible with PMBus 1.3.1 Specification
• Full PMBus Master and Slave functionality
• Supports all PMBus command codes as per the specifications
• Supports programmable clock frequency of operation
• Supports Timeout detection and generation
• Supports Alert generation and handling
• Supports Bus-accurate timing
• Supports Packet Error Checking(PEC)
• Supports Master/Slave arbitration and clock synchronization
• Supports Glitch insertion and detection
• Supports Fault Management and Reporting feature
• Supports re-synchronization of Slave
• Supports injection of errors and detection
• Master abort in middle of transaction
• Master doing ACK on last read access
• Master continue on NACK after write NACK from Slave
• Random and periodic clock period stretching by Slave
• Random write NACK insertion error by Slave
• Packet error check(PEC) error
• NACK for PEC code by Slave
• ACK for PEC code by Master
• Master asserted stop condition before PEC byte
• NACK for Command code byte by Slave
• NACK for second address byte after repeated start to same Slaves
• NACK for write size byte
• NACK for read size byte
• More than expected bytes were sent or received
• Less than expected bytes were sent or received
• Number of bytes field and actual bytes don't match
• NACK for read data from Master for bytes which is not last byte
• Master is driving SCL after sending NACK for read data
• Wrong ARP address
• Unsupported command codes
• Glitch insertion
• Timeout error insertion
• Implements all the registers and commands as per the PMBus specification
• Compares read data with expected results
• Various kind of Master and Slave errors generation
• Status counters for various events in bus
• Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations
• PMBus Synthesizable Transactor comes with complete testsuite to test every feature of PMBus specification

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

• Synthesizable transactors
• Complete regression suite containing all the PMBus testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and functions used in verification env
• Documentation also contains User's Guide and Release notes