PMBUS Master IIP

PMBUS Master interface provides full support for the two-wire PMBUS Master synchronous serial interface, compatible with version 1.3.1 Part II of PMBus Bus Specification. Through its PMBUS Master compatibility, it provides a simple interface to a wide range of low-cost devices. PMBUS Master IIP is proven in FPGA environment. The host interface of the PMBUS Master can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

PMBUS Master IIP is supported natively in Verilog and VHDL

• Compliant with version 1.3.1 Part II of PMBus Bus Specification
• Supports HCI and Non HCI Interface
• Full PMBus Master Functionality
• Supports all the PMBus commands as per Specification
• Send byte command
• Write byte command
• Write word command
• Read byte command
• Read word command
• Block write command
• Block read command
• Block write and read process call command
• Supports Extended command protocol
• Supports Zone write and Zone read
• Supports General call address
• Supports Sending command to a group
• Supports PMBus device fault management
• Supports Packet Error checking
• Supports alert handling
• Supports Master arbitration and Clock synchronization
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The PMBUS Master interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User's Guide and Release notes.