Vendor: Cadence Design Systems, Inc. Category: Debug Trace

Simulation VIP for AMBA ATB

Cadence provides a mature and comprehensive Verification IP (VIP) for the Trace Bus (ATB) specification which is part of the Arm®…

Verification IP View all specifications

Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the Advanced Trace Bus (ATB) specification which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for ATB provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Cadence provides an integrated solution for interconnect verification that verifies the correctness and completeness of data as it passes through the system and performance analysis that provides automated generation of testbenches. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for ATB helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Supported specification: AMBA4 ATB v1.0 and v1.1.

Key features

  • Data Widths
    • All legal data widths
  • Automatic Subordinate Responses
    • Support to use automatic Subordinate responses
  • Delay Control
    • Control the delay between the items on the channels
  • Manager Signal Control
    • Control the values of the signals issued by the manager
  • Subordinate Response Control
    • Control over the values of the signals issued by the subordinate
  • Multiple Agents
    • Supports any number of agents
  • Transaction Types
    • Monitoring and driving of all transactions (data, flush, and sync)

Block Diagram

Specifications

Identity

Part Number
Simulation VIP for AMBA ATB
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Debug Trace IP core

How a Multi-Protocol PHY Simplifies Physical AI Connectivity

Physical AI systems must move large amounts of data across two very different connectivity domains. Accelerators and local storage need high-bandwidth, low-latency links close to the compute SoC, while sensors and control modules require reliable connectivity across the larger platform. Supporting both domains with separate high-speed PHYs can increase silicon area and integration complexity.

Building AI Infrastructure for Greater Choice and Flexibility

AI infrastructure is changing fast. Training and inference are putting different demands on compute, memory, connectivity, and networking, and there is no single architecture that fits every workload. For system architects, this opens up an important question: How much flexibility can be built into the system from the start?

Frequently asked questions about Debug Trace IP

What is Simulation VIP for AMBA ATB?

Simulation VIP for AMBA ATB is a Debug Trace IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Debug Trace?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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