SWD Verification IP

Truechip's SWD Verification IP provides an effective & efficient way to verify the components interfacing with ARM Debug Interface. It is fully compliant with the ARM Debug Interface Architecture v5 Specification (IHI0031A) by ARM Limited. This VIP is a lightweight VIP with an easy plug-and-play interface so that there is no hit on the design cycle time

• Compliant to ARM Debug Interface Architecture v5 (ADIv5) Specification IHI0031A
• Supports all types of SWD components — Master (Host) and Slave (Target)
• Wide range of ADIv5 protocol checks on SWCLK and SWDIO signals
• Configurable turnaround period (1/2/3/4 cycles) via WCR register
• Parameterized address width and data width configuration
• Support for all DP registers (IDCODE, CTRL/STAT, SELECT, ABORT, RDBUFF, RESEND, WCR)
• Support for all AP registers (CSW, TAR, DRW, BD0-BD3, IDR, BASE, CFG)
• Supports pipelined (posted) AP read transactions via RDBUFF
• Supports SWD write buffering for high throughput AP write sequences
• Supports overrun detection mode (ORUNDETECT) with STICKYORUN handling
• Supports pushed compare and pushed verify modes with MASKLANE control
• Supports TRNCNT (Transaction Counter) for bulk AP transaction sequences
• Sticky error flag detection and recovery (STICKYERR, STICKYORUN, WDATAERR)
• ABORT register support for sticky flag clearing & AP transaction abort
• DAP power domain management (CSYSPWRUPREQ/ACK, CDBGPWRUPREQ/ACK)
• Basic internal and external clock and reset modes
• Detailed transaction logs for data comparison and debugging
• Supports additional analysis port for custom scoreboard implementation
• Bus assertions for all possible protocol scenarios
• Provides detailed statistics for each transaction
• Provides a comprehensive user API (callbacks) in all BFMs

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality
• Availability of Compliance & Regression Test Suites
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and cover points with connectivity examples for all the components
• Consistency of interface, installation, operation and documentation across all our VIPs
• Provide complete solution and easy integration in IP and SoC environments

• SWD Master (Host) Agent
• SWD Slave (Target) Agent
• SWD Bus Monitor, Assertion Module and Scoreboard
• Test Environment and Test Suite:
  • Basic and directed protocol tests
  • Random Tests
  • Error Scenario Tests
  • RAL Tests
  • Dynamic Tests
  • Assertion and cover-point Tests
• Integration Guide, User Manual, FAQ and Release Notes