Vendor: SmartDV Category: Debug Trace

AMBA ATB Synthesizable Transactor

AMBA ATB Synthesizable Transactor provides a smart way to verify the AMBA ATB component of a SOC or a ASIC in Emulator or FPGA pl…

Overview

AMBA ATB Synthesizable Transactor provides a smart way to verify the AMBA ATB component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's AMBA ATB Synthesizable Transactor is fully compliant with standard ARM AMBA 3 ATB (ATB v1.0) and AMBA 4 ATB (ATB v1.1) Specification and provides the following features

Key features

  • Compliant to ARM AMBA 3 ATB (ATB v1.0) and AMBA 4 ATB (ATB v1.1) Protocol.
  • Support AMBA ATB Master, ATB Slave and ATB Checker.
  • Support for multiple masters and slaves.
  • Supports all ARM AMBA ATB 1.0/1.1 data, byte and ID widths.
  • ATB 1.0/ATB 1.1 common support
    • Supports Flow control - valid/ready signaling for trace data.
    • Supports different types of Flush Request control - Flush valid/ready signaling with trace data.
    • Support for programmable delays.
    • Supports capturing of valid trace data.
    • Supports constrained randomization of protocol attributes.
    • Flexibility to send completely configured data.
    • Programmable ID's for the trace transfers.
    • Programmable Timeout insertion.
    • Ability to inject errors during data transfer.
  • ATB 1.1 support
  • In addition to ATB 1.0 support, ATB 1.1 supports the following features,
    • Supports enable and disable access for clock.
    • Supports Synchronization Request operations.
    • Supports trace triggering operations.
  • Rich set of configuration parameters to control AMBA ATB functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings,timing and protocol violations.
  • Status counters for various events on bus.
  • AMBA ATB SimXL comes with complete testsuite to test every feature of ARM AMBA ATB 1.0/1.1 specification

Block Diagram

AMBA ATB Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV VIP's.
  • All UVM sequences/testcases written with VIP can be reused.
  • Runs in every major emulators environment.
  • Runs in custom FPGA platforms.

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the AMBA ATB testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
AMBA ATB Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

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Frequently asked questions about Debug Trace IP

What is AMBA ATB Synthesizable Transactor?

AMBA ATB Synthesizable Transactor is a Debug Trace IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Debug Trace?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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