Vendor: Synopsys, Inc. Category: Debug Trace

Verification IP for AMBA ATB

Synopsys Verification IP (VIP) for Arm® AMBA® ATB™ provides a comprehensive set of protocol, methodology, verification, and produ…

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Overview

Synopsys Verification IP (VIP) for Arm® AMBA® ATB™ provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of Arm AMBA ATB based designs.

Key features

  • Trace Data Transfer (Valid, ready signaling) 
  • Narrow Trace Data Transfer (Data Valid Bytes signaling) 
  • Flow Control (Valid, ready signaling) 
  • Flush Request Response (Flush Valid, Ready signaling with Data transfer) 
  • Synchronization Request capture and pass to Trace Source (i.e. Sequence layer) 
  • Secondary Random Response for Trace Data Transfer 
  • Secondary Random Flush Request Generation 
  • Secondary Random Synchronization Request Generation 
  • Secondary Memory (for Trace Data capture)

Block Diagram

Verification IP for AMBA ATB block diagram

Benefits

  • Native SystemVerilog/Verilog with UVM
  • Includes primary, secondary, monitor
  • Runs natively on all major simulators
  • Built-in UVM sequence library
  • Verdi® protocol aware debug

Specifications

Identity

Part Number
Verification IP for AMBA ATB
Vendor
Synopsys, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA
Contact Synopsys, Inc.

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Frequently asked questions about Debug Trace IP

What is Verification IP for AMBA ATB?

Verification IP for AMBA ATB is a Debug Trace IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this Debug Trace?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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