Vendor: SmartDV Category: Debug Trace

AMBA ATB Assertion IP

AMBA ATB Assertion IP provides a smart way to verify the AMBA ATB component of a SOC or an ASIC.

Overview

AMBA ATB Assertion IP provides a smart way to verify the AMBA ATB component of a SOC or an ASIC. The SmartDV's AMBA ATB Assertion IP is fully compliant with standard AMBA ATB 1.0/1.1 Specification.

AMBA ATB Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA ATB Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Compliant to ARM AMBA 3 ATB (ATB v1.0) and AMBA 4 ATB (ATB v1.1) Protocol.
    • Supports all ARM AMBA ATB data, byte and ID widths.
    • Supports Flow control and Flushing
    • Supports for ATB1.1 Synchronization Request and triggering operations.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV ATB VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure ATB Assertion IP functionality.

Block Diagram

AMBA ATB AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
AMBA ATB AIP
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Debug Trace IP core

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As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

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To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about Debug Trace IP

What is AMBA ATB Assertion IP?

AMBA ATB Assertion IP is a Debug Trace IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Debug Trace?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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