HDCP 1.x Receiver IIP
HDCP 1.x Receiver core is compliant with standard HDCP specification as 1.3 and 1.4.
Overview
HDCP 1.x Receiver core is compliant with standard HDCP specification as 1.3 and 1.4. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. HDCP 1.x Receiver IIP is proven in FPGA environment. The Receiver interface of the HDCP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
HDCP 1.x Receiver IIP is supported natively in Verilog and VHDL
Key features
- Supports HDCP version 1.3 and 1.4 Specifications.
- Supports full HDCP Receiver functionality.
- Fully synthesizable.
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready.
- Simple interface allows easy connection to microprocessor/microcontroller devices.
- Supports HDCP Receiver functionality for Display Port, HDMI and MHL content interfaces.
- User keys can be loaded for Authentication.
- Supports 8/16/24/32 bit width cipher output.
- Supports Authentication Protocol.
- Supports Encryption Status Signaling.
- Enhanced Encryption Status Signaling (EESS).
- Original Encryption Status Signaling (OESS).
- Supports System Renewability Message (SRM) and Revocation.
- Supports SHA-1 Algorithm for Authentication.
- Supports HDCP RNG Functions.
Block Diagram
Benefits
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
What’s Included?
- The HDCP 1.x Receiver interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about HDCP IP core
HDCP 2.2 Authentication: RSA Cryptography
The HDCP 2.2 Authentication Process - an Introduction
Video content protection using secure embedded non-volatile memory for HDMI with HDCP
Rethinking Display Safety: Why RISC-V-Supervised DisplayPort Subsystems Enable Secure, Isolated Automotive Architectures
Understanding LTTPR: Enabling High-Speed DisplayPort Interconnects in Complex System Designs
Frequently asked questions about HDCP IP cores
What is HDCP 1.x Receiver IIP?
HDCP 1.x Receiver IIP is a HDCP IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this HDCP?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HDCP IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.