Vendor: Synopsys, Inc. Category: Random Number Generator

True Random Number Generators

The security strength of many systems and applications is dependent on the quality of random number generators.

Overview

The security strength of many systems and applications is dependent on the quality of random number generators. Many cryptographic operations require a source of random numbers, such as the creation of cipher keys and initial values for counters and protocol parameters.
The Synopsys True Random Number Generator (TRNG) is classified as a Non-deterministic Random Bit Generator (NRBG) using the terminology preferred by the National Institute of Standards and Technology (NIST). The noise source does not depend on process-specific circuitry and is therefore very portable across different ASIC and FPGA fabrication technologies.

Benefits

  • Designed for compliance with FIPS 140-2/140-3 and OSCCA certifications
  • Customer configurable
  • Area: 15-20K ASIC gates
  • Performance: 125 Mbps at 500 MHz
  • Wide system clock dynamic range
  • Redundant internal seed generators
  • Selectable number of seed generators: 6 or 8
  • Automatic and manual reseeding
  • Two independent background automatic reseed modes
  • Shift register compatible output stream for auxiliary uses: Differential power analysis; Timing analysis
  • Interfaces: Memory mapped (AXI/AHB/APB); Serial random bit stream; Nonce interface compatible with Synopsys HDCP Content Protection ESMs

Applications

  • Security protocols
  • Networking
  • MobileConsumer electronics
  • IoT
  • Automotive
  • Government/Military

What’s Included?

  • Verilog HDL developed in compliance with the IEEE 1364 Verilog-2005 standard
  • Testbench and test vectors
  • Sample synthesis script and constraints
  • Sample simulation script
  • Documentation
  • Reference software development kit (SDK)

Specifications

Identity

Part Number
dwc_true_random_number_generators
Vendor
Synopsys, Inc.
Type
Silicon IP

Security

RNG Type
TRNG

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Random Number Generator IP core

Generating AMD microcode stimuli using VCS constraint solver

As microprocessor designs have grown considerably in complexity, the use of hand-written directed tests in verification has dwindled. In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. We present and analyze the method and discuss its effectiveness in today’s verification environment.

Accelerated SoC Verification with Synopsys Discovery VIP for the ARM AMBA 4 ACE Protocol

This paper describes how a reference verification platform built with the Discovery VIP for the AMBA ACE protocol can be utilized to accelerate the verification of multi-core SoCs. Also highlighted are Synopsys verification technologies like Discovery Visualization Environment (DVE) and Protocol Analyzer for advanced debug of the AMBA 4 AXI/ACE protocols.

Functional Coverage Analysis for IP Cores and an Approach to Scaledown Overall Simulation Time

This paper presents functional coverage analysis automation and an approach to scale down overall simulation time. It is well known that functional verification of configurable IP cores is a real challenging task in any digital design development. Consequently, it is necessary to develop new methodologies to improve the quality of functional verification and also to decrease the time for regression convergence.

Advanced Power Management in Embedded Memory Subsystems

This paper addresses minimizing low-power design complexity with power, performance and density optimized IP. It covers the power problem, and the complexity of designing with multiple power domains in SoC designs that contain embedded memory. The paper includes the trade-offs and benefits of various power management features as well as the implementation of the design for superior testability by providing optimal test resource partitioning.

Frequently asked questions about Random Number Generator IP cores

What is True Random Number Generators?

True Random Number Generators is a Random Number Generator IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this Random Number Generator?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Random Number Generator IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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