AES-XTS Muti-Booster

The AES-XTS Multibooster crypto engine includes a generic & scalable implementation of the AES algorithm making the solution suitable for a wide range of low-cost & high-end applications (including key, tweak, input and output registers and Galois field multiplier).

This crypto engine targets high-performance applications, where a high throughput is required. Thanks to its scalability, it can be tailored to reach the best trade-off between performances, area and technology.

Implementation aspects

Data The AES-XTS crypto engine is easily portable to ASIC and FPGA . It supports a wide range of applications on various technologies. The unique architecture enables a high level of flexibility. The throughput and features required by a specific application can be taken into account in order to select the most optimal and compact configuration.

• ASIC & FPGA
• High throughput:
  • ASIC: 2Tbps
  • FPGA: 100 Gbps
• 128-bit and 256-bit key
• NIST SP 800-38D compliant
• Scalable solution
• Can be provided with AXI DMA & software
• Cipher stealing (optional)
• Low power feature
• Best trade-off between area and performance
• Straight forward integration with simple FIFO interfaces

• Easy to integrate
• Tunable solution
• Fully digital
• AMBA interface
• Strong technical support

• Encrypted disk/data storage
• SATA III

• Netlist or RTL
• Scripts for synthesis & STA
• Self-checking RTL test-bench on referenced vectors
• Documentation