Advanced Encryption Standard Cryptographic Co-Processor

The DAES IP Core  is a high-performance AES hardware accelerator designed to execute Advanced Encryption Standard (AES) operations with exceptional speed, reliability, and energy efficiency. Optimized for embedded systems, SoCs, FPGA designs, and other security-critical applications, the DAES IP Core significantly offloads computationally intensive AES tasks from the main processor, enhancing both system performance and power efficiency.

Supporting AES-128 and AES-256 encryption and decryption, the DAES IP Core is fully compatible with all major block cipher modes, including:

• ECB (Electronic Codebook)
• CBC (Cipher Block Chaining)
• CFB (Cipher Feedback)
• OFB (Output Feedback)
• CTR (Counter Mode)

Engineered for modern cryptographic workloads, DAES automatically manages the complete data flow for all supported modes. Software is only responsible for basic data I/O, reducing development complexity and eliminating performance bottlenecks. The core also includes automatic key expansion for both encryption and decryption, ensuring secure and consistent operation across applications like secure communication systems, encrypted data storage, industrial IoT, and edge computing.

The DAES IP Core implements the Rijndael encryption algorithm, fully compliant with FIPS 197 Advanced Encryption Standard. With AES being one of the most widely deployed block ciphers — from IoT devices and automotive systems to telecommunications equipment and cloud servers — its hardware implementation offers substantial advantages in performance, latency, and resistance to side-channel attacks compared to software-only solutions.

• AES encryption and decryption support
• Support for 128-bit and 256-bit keys
• Block cipher modes support:
  • ECB (Electronic Codebook)
  • CBC (Cipher Block Chaining)
  • CFB (Cipher Feedback)
  • OFB (Output Feedback)
  • CTR (Counter)
•  Configurable support for selected modes and key sizes
• Flexible, generic memory-mapped interface for easy integration with:
  • AMBA – APB / AHB / AXI Bus
  • Avalon Bus
  • OPB BUS

• High-performance hardware acceleration for AES-128 and AES-256
• Support for multiple block cipher modes
• Automatic data flow and key management, reducing software overhead
• Seamless integration into FPGA and ASIC environments
• Ideal for security-critical embedded and IoT designs
• Compatible with AMBA APB, AHB, AXI, offering easy system-level integration

•  Verilog HDL Source Code
•  Test-bench environment
•  Tests with reference responses
•  Synthesis scripts
•  Example C software driver library
•  Technical documentation
•  Technical support