UCIe IP Listing

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…

• UCIe

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…

• UCIe

The UCIe IP solution includes D2D Adapter layer which supports streaming/PCIe/CXL/Raw flitformats, supports both standard and mai…

• UCIe

Industry , Silicon Proven, 32 Gbps per pin, backed by a portfolio of verification tools, PHY interoperability and integration.

• UCIe

Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Univer…

• Verification IP

The UCIe Verification IP provides an effective & efficient way to verify the UCIe components of an IP or SoC.

• Verification IP

The UCIe 2.0 Verification IP offers a streamlined and efficient solution for verifying UCIe components within an IP or SoC.

• Verification IP

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…

• UCIe

Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for …

• UCIe

The UCIe PHY & D2D Adapter IP portfolio includes 32Gbps UCIe- (UCIe-A) & Standard (UCIe-S) cores as per the latest UCIe v1.1 spec…

• UCIe

Support for multiple protocol PCIE/CXL/Streaming

• UCIe
• Immediate
• UCIE 1.0

High-Performance AXI to UCIe FDI Interface IP for Scalable System Integration

• UCIe

The core idea behind the Universal PHY is to enable open chiplets for a broad range of applications.

• BOW

The SLM Signal Integrity Monitor (SIM) IP enables signal quality measurement for die-to-die interfaces.

• Monitoring

Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hypers…

• PHY

Compliant with the UCIe Specification Revision 1.1

• PHY
• UCIe 1.1

UCIe PHY IP with X16 data width for standard package and up to 8 Gbit/s per pin data rate

• GlobalFoundries
• 22nm
• FDX

Early adopter version of the upcoming revision of the JEDEC standard for Serial Interface for Data Converters The JESD204E Contro…

• JESD204

IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face package.

• TSMC
• 5nm
• N5FF

Accelerated confidence in simulation-based verification of RTL designs with PCI Express (PCIe) interfaces: PCIe Gen2/3/4/5/6/7 Av…

• Verification IP