UCIe PHY & Controller
Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for …
Overview
Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for highest performance with the lowest power and area overhead that is compliant to the Universal Chiplet Interconnect Express (UCIe) 2.0 specification.
Key features
- Supports transfer rates of up to 32 Gbps/pin for up to 8Tbps with 10.5Tbps/mm of die edge bandwidth
- Supports PCIe, CXL and streaming protocols adaptable to any communication protocols including extending the vendor's Non-Coherent and Coherent NOC interconnects across multiple dies
- Built-in link initialization
- Supports major 2.5D inter-die packaging technologies and standard packaging technologies
- Supports internal and external (PHY-to-PHY) loopback test
- Supports built-in self-test and repair functionality to maximize post-package yield
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about UCIe IP core
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Frequently asked questions about UCIe IP cores
What is UCIe PHY & Controller?
UCIe PHY & Controller is a UCIe IP core from SkyeChip listed on Semi IP Hub.
How should engineers evaluate this UCIe?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UCIe IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.