Synopsys Advances Die‑to‑Die Connectivity with 64G UCIe IP Tape‑Out
Discover Synopsys 64G UCIe IP for energy-efficient, high-bandwidth die-to-die connectivity in advanced multi-die AI and HPC designs.
Vendor:
SkyeChip
Category:
UCIe
UCIe PHY & Controller
Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for …
Overview
Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for highest performance with the lowest power and area overhead that is compliant to the Universal Chiplet Interconnect Express (UCIe) 2.0 specification.
Key features
- Supports transfer rates of up to 32 Gbps/pin for up to 8Tbps with 10.5Tbps/mm of die edge bandwidth
- Supports PCIe, CXL and streaming protocols adaptable to any communication protocols including extending the vendor's Non-Coherent and Coherent NOC interconnects across multiple dies
- Built-in link initialization
- Supports major 2.5D inter-die packaging technologies and standard packaging technologies
- Supports internal and external (PHY-to-PHY) loopback test
- Supports built-in self-test and repair functionality to maximize post-package yield
Specifications
Identity
Part Number
UCIe PHY & Controller
Vendor
SkyeChip
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Malaysia
Learn more about UCIe IP core
Cadence Tapes Out 32GT/s UCIe IP Subsystem on Samsung 4nm Technology
In keeping with a rapidly broadening portfolio of die-to-die connectivity solutions, Cadence has taped out its IP subsystem for 32GT/s UCIe solution on Samsung's 4nm (SF4X) process technology.
UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
Understand the role of the UCIe D2D Adapter in enabling reliable, scalable, multi-protocol die-to-die communication for chiplet architectures.
The Next-Generation UCIe IP Subsystem for Advanced Package Designs
Cadence announces that it has taped out its IP subsystem for the 32G UCIe advanced package on TSMC’s 3nm (N3P) process technology.
Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process
Cadence has successfully demonstrated first-pass silicon success of its UCIe™ standard package IP on Samsung Foundry's 5nm automotive process. This milestone underscores Cadence's commitment to delivering high-performance, automotive-grade IP solutions that meet the stringent requirements of next-generation automotive and high-performance computing applications.
40G UCIe IP Advantages for AI Applications
For AI workloads to be processed reliably at a fast rate, the die-to-die interface in multi-die designs must be robust, low latency, and most importantly high bandwidth. This article outlines the need for 40G UCIe IP in AI data center chips leveraging multi-die designs.
Frequently asked questions about UCIe IP cores
What is UCIe PHY & Controller?
UCIe PHY & Controller is a UCIe IP core from SkyeChip listed on Semi IP Hub.
How should engineers evaluate this UCIe?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UCIe IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.