Vendor: Arteris Category: Network-On-Chip

FlexNoC Interconnect IP

Physically aware network-on-chip IP designed to speed development.

Overview

Physically aware network-on-chip IP designed to speed development.

FlexNoC® Interconnect IP is used by the world’s top semiconductor design teams as the backbone for on-chip communications in chips that target the fastest growing markets. It enables efficient data movement and provides flexibility in complex designs. FlexNoC benefits include:

  • Accelerate development cycles
  • Increase system performance
  • Reduce latency
  • Improve quality of results
  • Increase power efficiency

Using both FlexNoC and Ncore IP in an ASIC design also delivers unparalleled performance optimization, scalability, and system integration. This in turn supports market differentiation and helps accelerate time to market.

Key features

  • Auto-timing closure assist
  • NIU (Network Interface Unit) tiling to organize NIUs into modular, repeatable blocks, improving scalability, efficiency, and reliability
  • Topology visualized directly on floorplan
  • Multi-clock/power/voltage domains and power management with unit-level clock gating
  • Multi-protocol support including AMBA 5 with QoS bandwidth regulator and limiter enumerations
  • General optimizations for lower area e.g. up to 30% for some NoC elements depending on configuration
  • Native and user-defined firewall security
  • Import and export to Magillem tools
  • AMBA 5 support of DVM 8.1 (Distributed Virtual Memory)
  • On-chip performance monitoring and debug
  • Debug and trace with ATB 128b and timestamps

Block Diagram

FlexNoC 5 block diagram

Benefits

Flexible topologies

FlexNoC is generated from simple elementary components, combined using a powerful set of underlying algorithms and an intuitive GUI, making it possible to build any topology.

Small to large SoCs

FlexNoC easily supports long cross-chip paths by leveraging source-synchronous communications and virtual channels.

Huge bandwidth

FlexNoC drives performant on-chip data flow and access to off-chip memory by enabling multichannel HBMx memory and high-bandwidth data paths.

Applications

  • Automotive,
  • Mobility,
  • Wireless,
  • Consumer Electronics,
  • IoT,
  • Server,
  • Networking and Industrial SoCs

What’s Included?

  • FlexNoC 5 Physically Aware Interconnect IP
  • Configuration tools
  • Automated testbench generator
  • Documentation, training, and support.
  • Safety Manual -- when licensed with the Functional Safety (FuSa) Option

Specifications

Identity

Part Number
FlexNoC Interconnect IP
Vendor
Arteris
Type
Silicon IP

Videos

Arteris FlexNoC 5 Physically Aware Network-on-Chip IP
Arteris unveils next-generation FlexNoC 5 physically aware network-on-chip IP. Get up to 5X faster physical convergence vs manual physical iterations and achieve PPA goals within schedule and budget constraints.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Arteris
HQ: United States

Learn more about Network-On-Chip IP core

How Cache Coherency Simplifies AI Software

This article explains how hardware-managed cache coherency can simplify AI software by coordinating shared data across CPUs, accelerators and chiplets. The article highlights the role of coherent and non-coherent interconnects in building scalable, efficient AI SoCs, while presenting Arteris’ Ncore, FlexNoC and FlexGen IP as complementary solutions for managing data movement.

Frequently asked questions about NoC IP cores

What is FlexNoC Interconnect IP?

FlexNoC Interconnect IP is a Network-On-Chip IP core from Arteris listed on Semi IP Hub.

How should engineers evaluate this Network-On-Chip?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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