USB 2.0 OTG PHY IP, UMC 40nm LP process
OTG USB2.0 UMC 40 nm LP/RVT process.
- USB 2.0
- UMC
- 40nm
- LP
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
USB 2.0 OTG PHY IP, UMC 40nm LP process
OTG USB2.0 UMC 40 nm LP/RVT process.
USB 2.0 OTG PHY IP, UMC 0.25um process
USB 2.0 host On-The-Go PHY, UMC 0.25um Logic process.
USB 2.0 OTG PHY IP, UMC 0.18um G2 process
USB 2.0 On-The-Go PHY, UMC 0.18um GII Logic RVT/FSG process.
USB 2.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB 2.0 On-The-Go PHY, UMC 0.13um HS/FSG Logic process.
USB 2.0 Device PHY IP, UMC 0.18um G2 process
USB2.0 Analog PHY, UMC 0.18um GII Logic RVT/FSG process.
USB 2.0 Device PHY IP, UMC 0.18um G2 process
USB2.0 PHY (Pure device mode), UMC 0.18um GII Logic RVT/FSG process.
USB 2.0 Device PHY IP, UMC 0.13um LL/FSG process
USB 2.0 PHY, UMC 0.13um LL Logic process.
USB 2.0 Device PHY IP, Non-Crystal mode support, UMC 40nm LP process
USB 2.0 PHY, crystal-less option, UMC 40nm LP/RVT process.
USB 1.1.OTG PHY IP, UMC 0.13um HS/FSG process
0.13um OTG PHY, UMC 0.13um HS/FSG process.
USB 1.1 PHY IP, UMC 0.18um G2 process
USB 1.1 transceiver, UMC 0.18um GII Logic process.
USB 1.1 PHY IP, UMC 0.18um G2 process
USB 1.1 PHY, UMC 0.18um GII Logic process 1.8/3.3V.
SATA II PHY IP, UMC 55nm SP process
Serial ATA I, II PHY, UMC 55nm SP/RVT Low-K Logic process.
MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process
MIPI Transmitter 80Mbps~1.5Gbps, UMC 40nm LP/RVT/LVT Low-K process.
MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process
MIPI Transmitter 80Mbps~1.5Gbps with 1-clock lane, 2-data lanes, UMC 40nm LP/RVT/LVT Low-K process.
MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process
MIPI Transmitter 80~1500MHz with 1-clock lane, 4-data lanes, UMC 40nm LP/RVT/LVT Low-K process.
MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process
MIPI Transmitter 80Mbps~1500Mbps combo with CMOS input, UMC 40nm LP Low-K process.
MIPI D-PHY Receiver IP, 80Mbps - 1.5Gbps, UMC 40nm LP process
MIPI Receiver 80Mbps-1.5Gbps, UMC 40nm LP Low-K Logic process.
LVDS Receiver IP, 500Mbps, UMC 55nm LP process
LVDS RX IO PAD 500Mbps, UMC 55nm LP/RVT Low-K Logic process.
SATA II PHY IP, UMC 0.13um HS/FSG process
3G/1.5G Serial ATA PHY, UMC 0.13um HS/FSG Logic process.
SATA II PHY IP, UMC 0.11um HS/FSG process
3G/1.5G Serial ATA PHY, UMC 0.11um HS/FSG Logic process.