MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process
MIPI Receiver 80Mbps-1Gbps, Combo PHY for MIPI & HiSPi & LVDS & SubLVDS, UMC 40nm LP Low-K Logic process.
- MIPI D-PHY
- UMC
- 40nm
- LP
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process
MIPI Receiver 80Mbps-1Gbps, Combo PHY for MIPI & HiSPi & LVDS & SubLVDS, UMC 40nm LP Low-K Logic process.
MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process
MIPI Receiver 80Mbps-1Gbps, UMC 40nm LP Low-K Logic process.
PCIe 3.1 PHY (6nm, 7nm, 12nm, 14nm, 16nm, 22nm, 28nm and 40nm)
M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
VeriSilicon GSMC 0.18um 1.8v/3v/5v Mult IO for SIMcard
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (08) Library developed by VeriSilicon is optimized for Grace Semiconductor Ma…
UniPro 2.0 & Silicon Proven v1.8, v1.61
IP
The USB1.1 PHY is an IP version of USB transceiver.
The 10G/1G dual-mode Ethernet MAC offers an IEEE802.3-2008 (802.3ae) compliant solution that meets the requirements for 10Gbps LA…
40G Ethernet Solution (MAC + 40GBase-R PCS)
The 40Gbps Ethernet IP solution offers a fully integrated IEEE802.3ba compliant package for NIC (Network Interface Card) and Ethe…
40/100G Dual Mode Ethernet Solution
The dual-mode 100Gbps/40Gbps Ethernet IP solution offers a fully integrated IEEE802.3ba compliant package for NIC (Network Interf…
LogiCORE IP Serial RapidIO Gen 2
The LogiCORE™ IP Serial RapidIO Gen 2 Endpoint solution, designed to RapidIO Gen 2.1 specification, comprises of a flexible and o…
Included at no additional charge with Vivado and ISE Design Suite The AXI Interconnect IP connects one or more AXI memory-mapped …
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
Noesis Technologies ntT1_G704 Framer/Deframer is designed for T1 networks and is compliant with ITU recommendations G.704, G.706,…
USB 3.0 OTG PHY IP, UMC 90nm SP process
USB 3.0 Transceiver, UMC 90nm SP/RVT Low-K Logic process.
USB 3.0 OTG PHY IP, UMC 55nm SP process
USB3.0 PHY, UMC 55nm SP/RVT Low-K Logic process.
USB 3.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB3.0 OTG PHY, UMC 0.13um HS/FSG Logic process.
USB 3.0 OTG PHY IP, UMC 0.11um HS/FSG process
USB3.0 PHY, UMC 0.11um HS/FSG (Cu) Logic process.
USB 3.0 OTG PHY IP, UMC 0.11um HS/AE process
USB3.0 PHY, UMC 0.11um HS/AE Logic process.
USB 2.0 OTG PHY IP, UMC 90nm LL process
USB2.0 OTG PHY, UMC 90nm LL Low-K -RVT process 2.5V OD 3.3V.