The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process
- UMC
- 40nm
- LP
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process
Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Enhancement) Logic Process
UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format
3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process
3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Proce…
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process
0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature.
0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature.
10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
XTAL LESS for USB3.0 ; UMC 40nm LP/RVT Logic Process
XTAL LESS for USB3.0 ; UMC 40nm LP/RVT Logic Process
10G TCP+UDP Offload+EMAC+PCIe+Host IF Ultra-Low Latency (SXTOE+UOE+PCIe)
INT 25012 is the only SOC IP Core that implements a full 10G bit TCP and UDP Stack in Handcrafted, Ultra-High Performance, , Flex…
10G TCP+UDP Offload+EMAC+Host_IF Ultra-Low Latency (SXTOE+UOE)
INT 25011 is the only SOC IP Core that implements a full 10G bit UDP Stack in Handcrafted, Ultra-High Performance, , Flexible and…
1G TCP Offload Engine TOE+MAC+PCIe+Host_IF Ultra-Low Latency (STOE+PCIe)
INT 2012 is the only SOC IP Core that implements a full 1G bit TCP Stack in Handcrafted, Ultra Low Latency and Very High Performa…
1G TCP Offload Engine TOE+MAC+Host_IF Ultra-Low Latency (STOE)
INT 1011 is the only SOC IP Core that implements a full 1G bit TCP Stack in Handcrafted, Ultra Low Latency and Very High Performa…
1G UDP Offload+MAC+PCIe+Host_IF Ultra-Low Latency (SUOE+PCIe)
INT 1512 is the only SOC IP Core that implements a full 1G bit UDP Stack in Handcrafted, Ultra High Performance, , Flexible and S…
1G_UDP_Offload+MAC+Host_IF Ultra-Low Latency (SUOE)
INT 1511 is the only SOC IP Core that implements a full 1G bit UDP Stack in Handcrafted, Ultra High Performance, , Flexible and S…
Ultral-small size: 0.033mm2; High performance, low EMI TX driver design
EDP_RX consists of electrical sub-blocks of main-link and AUX channel of PHY for eDP RX.
eDP (Embedded Displayport) receiver Link/PCS IP core is compliant with eDP 1.4a/DP 1.3 specification.
LVDS 10 bits dual port transmitter
IP
USB 2.0 Device PHY IP, UMC 0.11um eFlash process
UMC 0.11um eFlash Process , USB 2.0 OTG PHY