MIPI M-PHY IP, UMC 40nm LP process
MIPI MPHY 6Gbps/lane, UMC 40nm LP Low-K process.
- MIPI M-PHY
- UMC
- 40nm
- LP
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
MIPI M-PHY IP, UMC 40nm LP process
MIPI MPHY 6Gbps/lane, UMC 40nm LP Low-K process.
LVDS RX, UMC 40nm LP/RVT Low-K Logic process.
64-bit Initiator/Target for PCI-X & 32- and 64-bit Initiator/Target for PCI
DO-DI-PCIX64-VE rolls the Initiator/Target for PCI ™/PCI-X ™, 32-bit Initiator/Target for PCI and 64-bit Initiator/Target for PCI…
With this core, the Xilinx Universal Serial Bus 2.0 High Speed Device provides a control interface to internal registers via a 32…
The Xilinx® LogiCORE™ IP JESD204 PHY core implements a JESD204B physical interface to simplify sharing serial transceiver channel…
PCIe 2.1 PHY(12nm,14nm, 16nm, 28nm, 40nm, 55nm)
M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
MIPI D-PHY RX/TX v1.1 / v1.2 IP in TSMC (12/16nm, 28nm, 40nm, and 55nm process)
The D-PHY is a popular MIPI physical layer developed for mobile applications because it is a flexible, high-speed, low-power and …
IP
SMIC 130nm G LVDS 800Mbps Transmitter
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SMIC 130nm G LVDS 1.25Gbps Transmitter
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SMIC 130nm G LVDS 1.25Gbps Receiver
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IP
IP
SMIC 130nm G LVDS 800Mbps Receiver
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IP
10/100 Ethernet PHY IP, UMC 0.18um MS process
10/100 Base-TX Fast Ethernet PHY, UMC 0.18um MMC process.
10/100 Ethernet PHY IP, UMC 0.13um HS/FSG process
10/100 Base-TX Fast Ethernet PHY, UMC 0.13um HS/FSG Logic process.
USB 3.0 OTG PHY IP, UMC 40nm LP process
USB 3.0 PHY, UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT process.
USB 3.0 Device PHY IP, Non-Crystal mode support, UMC 40nm LP process
Crystal-less USB 3.0 PHY, UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT process.
USB 2.0 OTG PHY IP, UMC 55nm eFlash process
USB2.0 OTG PHY, UMC 55nm eFlash process.