Vendor: PRSsemicon Group Category: I2C / I3C

MIPI I3C MASTER

Key features

  • Compliant with the MIPI Alliance Draft Specification for I3C v1.x
  • I3C Master Features
    • Supports all modes of Master – SDR, HDR and HDR-DDR,I2C Modes
    • Can be configured to work as secondary master also.
    • Dynamic addressing assignment capability
    • Support for slave generated inband interrupts.
    • Memory for retaining bus device addresses.
  • I3C Slave Features
    • Supports I3C slave configuration – HDR-DDR Slave, SDR Only Slave.
    • Common Slave IP can be instantiated many times to have multiple slaves on the I3C bus.
    • Dynamic address complaint.
    • Supports/Tolerate I3C global command codes.
    • Master Interface for system access : APB. Optionally AXI.
    • Slave Interface for Register access : APB
    • Configurable FIFOs

Block Diagram

MIPI I3C MASTER block diagram

Specifications

Identity

Part Number
MIPI I3C MASTER
Vendor
PRSsemicon Group
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

PRSsemicon Group
HQ: India

Frequently asked questions about I2C / I3C IP cores

What is MIPI I3C MASTER?

MIPI I3C MASTER is a I2C / I3C IP core from PRSsemicon Group listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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