Vendor: Lattice Semiconductor Corp. Category: MIPI

Four Input to One Output MIPI CSI-2 Camera Aggregator Bridge

Many new applications such as augmented reality, depth perception and gesture recognition require multiple image sensor interface…

Overview

Many new applications such as augmented reality, depth perception and gesture recognition require multiple image sensor interfaces to connect to the application processor with minimal latency between frames. Lattice Crosslink can interface to multiple MIPI CSI-2 image sensors and aggregate data to a single CSI-2 output. Aggregation can be performed by stitching the image sensor frames together in a side by side configuration or arbitrating data packets based on virtual channel.

Lattice CrossLink is a programmable video interface bridging device capable of providing multiple MIPI CSI-2 interfaces at up to 6 Gbps per PHY. This bridge is available as free IP in Lattice Diamond for allowing easy configuration and setup.

Features * Supports MIPI CSI-2 inputs and outputs at up to 6 Gbps: 1, 2 or 4 Data Lanes
* Merges two of four MIPI CSI-2 inputs to one MIPI CSI-2 output * GPIO provides mux control to switch between two sets of merged CSI-2 inputs
* Output data rate is 2x input data rate
* LR merge method – Combined or merged packets from both left and right channels to form a single packets for each pixel line
* VC merge method – Assigned a unique virtual channel ID for each channel, data will be sending alternately between channels. AP is responsible to perform the actual merging between channels



* Supports all CSI-2 data type: RAW, RGB, YUV
* Compliance with MIPI D-PHY Specification v1.1
* Compliance with CSI-2 Specification v1.1

Key features

  • Supports MIPI CSI-2 inputs and outputs at up to 6 Gbps: 1, 2 or 4 Data Lanes
  • Merges two of four MIPI CSI-2 inputs to one MIPI CSI-2 output
    • GPIO provides mux control to switch between two sets of merged CSI-2 inputs
    • Output data rate is 2x input data rate
    • LR merge method – Combined or merged packets from both left and right channels to form a single packets for each pixel line
    • VC merge method – Assigned a unique virtual channel ID for each channel, data will be sending alternately between channels. AP is responsible to perform the actual merging between channels
  • Supports all CSI-2 data type: RAW, RGB, YUV
  • Compliance with MIPI D-PHY Specification v1.1
  • Compliance with CSI-2 Specification v1.1

Specifications

Identity

Part Number
4Inputto1OutputMIPICSI2CameraAggregatorBridge
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about MIPI IP core

M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C

With the rapid growth of AR/VR and high-resolution imaging systems such as drones and action cameras, MIPI CSI (Camera Serial Interface) and MIPI DSI (Display Serial Interface) require both high data throughput and low power consumption. M31 provides a MIPI C-PHY and D-PHY IP combo solution implemented on TSMC N3P and N3C processes.

MIPI CCI over I3C: Faster Camera Control for SoC Architects

Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.

MIPI MPHY 6.0: Enabling Next-Generation UFS Performance

High-speed chip-to-chip data transfer is continuously evolving to meet increasing performance demands. MIPI MPHY is a high-speed physical layer interface developed by the MIPI Alliance. This protocol is used for high-speed chip-to-chip interfaces, mainly in mobile and automotive devices.

MIPI: Powering the Future of Connected Devices

From the first monochrome mobile displays to today’s ultra-high-definition automotive dashboards and immersive AR/VR headsets, MIPI technology has quietly become the backbone of modern data connectivity. Let’s explore how MIPI standards have evolved, the markets they serve, and why Rambus is at the forefront of this transformation.

Frequently asked questions about MIPI IP cores

What is Four Input to One Output MIPI CSI-2 Camera Aggregator Bridge?

Four Input to One Output MIPI CSI-2 Camera Aggregator Bridge is a MIPI IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP