The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the highly-efficient ARCv2 instruction set architecture (ISA) and pipeline that deliver a high degree of performance efficiency and code density with minimal power and area for embedded applications. The ARC HS3x processors can be configured as dual core or quad core for maximum performance.
The HS34 processor is optimized for use in high-end embedded applications where real-time, deterministic response is desired, such as SSD controllers, baseband control, digital TV, home networking, automotive systems and smart appliances.
The HS36 processor has all the features of the HS34 and adds support for up to 64KB of instruction and data cache. The HS36 processors is ideally suited for high-performance embedded applications such as SSD controllers, networking, medical, and industrial & automotive systems.
The ARC HS38 processors is optimized for use in high-performance embedded applications running Linux. The processor has a full-featured Memory Management Unit (MMU) supporting a 40-bit physical address space and page sizes up to 16 megabytes (MBs), giving designers the ability to directly address a terabyte of memory with faster data access and higher system performance. It also supports SMP Linux, full Level 1 cache coherency and up to 8 MB of Level 2 cache.
To minimize system-level latency and increase overall system performance, the HS3x processors all support close coupled memories and direct mapping of peripherals, providing single-cycle access to other IP and memory blocks on the SoC. Native ARM® AMBA® AXI™ and AHB™ standard interfaces are configurable for 32-bit or 64-bit transactions to optimize throughput.
The ARC HS Family is supported by a robust ecosystem of software and hardware development tools, including the MetaWare Development Kit, a complete solution for developing, debugging, and optimizing embedded software on ARC processors, the MQX real-time operating system (RTOS) and a portfolio of third-party tools, operating systems and middleware from leading industry vendors through the ARC Access Program.
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L2 cache option for multicore versions of ARC HS36 and HS38 processors is a Coherency IP core from Synopsys, Inc. listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Coherency IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.