JTAG - CJTAG Verification IP

Truechip's JTAG - CJTAG Verification IP provides an effective & efficient way to verify the components interfacing with RISC-V Debug Module. It is fully compliant with standard IEEE 1149.1, IEEE 1149.6 and IEEE 1149.7. This VIP is a lightweight VIP with an easy plug-and-play interface so that there is no hit on the design cycle time.

• Compliant to RISC-V Debug Specification 0.13.2, JTAG provided by SiFive, Inc.
• Fully compatible with the IEEE 1149.7 (Compact JTAG) standard.
• Supports all types of JTAG components, master and slave ( TAP ).
• Wide range of IEEE 1149-1 2013 protocol checks.
• Configurable Instruction Register Widths ( 5 bits min )
• Configurable Data Registers ( Variable Widths )
• User-defined instructions ( Bypass, IDCODE, dtmcs, dmi )
• User-defined data register ( IDCODE, dtmcs, dmi )
• Supports 2-pin interface as specified in (CJTAG).
• Supports TAP.7 capability classes T0 to T5.
• Supports EPU for classes 0 to 3 & Supports APU for classes 4 & 5.
• Supports all mandatory and optional scan formats (JScan, Mscan, OScan, and Sscan).
• Supports user specific tasks for data loading and reading for on the fly debugging
• Support for all Test Access Port ( TAP ) pins
• Basic internal and external clock and reset modes
• Detailed transaction logs for data comparison and debugging
• Supports additional analysis port for custom scoreboard implementation
• Supports programmable data register encodings for use in future implementations
• Bus assertions for all possible scenarios.
• Provides detailed statistics for each transaction.
• Provides a comprehensive user API (callbacks) in all BFMs.

• Available in native SystemVerilog(UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure the highest level of quality.
• Availability of Compliance & Regression TestSuites.
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and cover pointswith connectivity example for all thecomponents.
• Consistency of interface, installation,operation, and documentation across all over.

eliverables

• VIP Master/Slave Agent.
• VIP Bus Monitor, assertion module and Scoreboard.
• Test Environment and Test Suite:
  • Basic and directed protocol tests.
  • Random Tests.
  • Error Scenario Tests.
  • Assertion and Cover-Point Tests
• Integration guide, User Manual, FAQ, and Release Notes.

• JTAG Driver BFM/Agent
• JTAG Monitor & Scoreboard
• JTAG Controller BFM/Agent
• Test-Bench Configurations
• Test Suite (Available in Source code)
  • Basic Protocol Tests
  • Directed & Random Tests
  • Assertions & Cover Point Tests
• Integration Guide, User Manual, and Release Notes