A design path to success exists for ultra-low-voltage SoCs
The alien realm of ultra-low voltage (ULV) in chip design means supply voltages near or below transistor threshold voltages.
Vendor:
Faraday Technology
Category:
Single-Protocol PHY
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.
Overview
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 55nm | SP | Pre-Silicon |
Specifications
Identity
Part Number
FXDLL341HF0A
Vendor
Faraday Technology
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Taiwan
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Frequently asked questions about Single-Protocol PHY IP
What is Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.?
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process. is a Single-Protocol PHY IP core from Faraday Technology listed on Semi IP Hub. It is listed with support for umc Pre-Silicon.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.