Nuclei System Technology
•
HQ:
China
The SPI (Serial Peripheral Interface) is a specialized communication interface targeting single, dual or quad SPI Flash memories.
- SPI / QSPI XSPI
Compare 589 Low-Speed Control Interface IP Cores from 76 vendors
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Protocol controller IP for a CAN FD light responder node
Robert Bosch GmbH• HQ: GermanyThe FDLR_CAN is a CAN IP module that can be implemented in an ASIC, FPGA, and mixed-signal device.It supports CAN FD light respon…
- CAN / CAN-FD / CAN-XL
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Protocol controller IP for Classical CAN / CAN FD / CAN FD light commander and CAN XL
Robert Bosch GmbH• HQ: GermanyThe XS_CAN is a low gate count CAN IP module that can be realized as stand-alone device, as part of an SoC, as part of an ASIC, o…
- CAN / CAN-FD / CAN-XL
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Verification IP for CAN XL, FD and CAN 2.0
Siemens Digital Industries Software• HQ: USAA comprehensive VIP solution portfolio for CAN XL, CAN FD and CAN 2.0 used by SoC and IP designers to ensure comprehensive verifi…
- Verification IP
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Synective Labs AB• HQ: Sweden
The IP is compliant to the new ISO 11898-1:2015 standard, supporting both standard CAN and CAN FD.
- CAN / CAN-FD / CAN-XL
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Arasan Chip Systems Inc.• HQ: USA
The MIPI I3CⓇ Total IP solution is a seamless integration of MIPI I3CⓇ controller, MIPI I3CⓇ PHY I/O, and MIPI I3CⓇ software stac…
- I2C / I3C
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Arasan Chip Systems Inc.• HQ: USA
The QSPI master core is easy to use, simple to work with, quick to operate, and reliable under all conditions.
- SPI / QSPI XSPI
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Arasan Chip Systems Inc.• HQ: USA
Classical CAN, also known as CAN 2.0 Bus Controller IP, is the foundational CAN bus standard.
- CAN / CAN-FD / CAN-XL
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Arasan Chip Systems Inc.• HQ: USA
The xSPI PHY is designed to work with both the xSPI/PSRAM and the xSPI master host controller IPs.
- SPI / QSPI XSPI
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CAST• HQ: USA
The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol.
- SENT
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CAST• HQ: USA
The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol.
- SENT
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Frontgrade Gaisler• HQ: Sweden
The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB.
- I2C / I3C
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Silicon Cores - a Div. of Silicon Interfaces• HQ: USA
UART eVC is a fully documented, off the shelf component for Cadence Specman Elite functional verification environment.
- UART
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Silicon Cores - a Div. of Silicon Interfaces• HQ: USA
The SafeSPI is a secure version of the SPI protocol that has been designed to provide enhanced security features, making it suita…
- SPI / QSPI XSPI
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Silicon Cores - a Div. of Silicon Interfaces• HQ: USA
The SPI protocol specification supports high speed data transfer as per the peripheral specification, making it ideal for high - …
- SPI / QSPI XSPI
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Silicon Cores - a Div. of Silicon Interfaces• HQ: USA
The I3c protocol, short for " Improved Inter - Integrated Circuit," is a communication protocol designed to improve upon the wide…
- I2C / I3C
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Silicon Cores - a Div. of Silicon Interfaces• HQ: USA
The I2C (Inter - Integrated Circuit) protocol is a widely used serial communication protocol for transferring data between electr…
- I2C / I3C
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Intel® Precision Time Protocol Servo (Intel® PTP Servo) FPGA IP
Altera• HQ: USACoordinate the actions of disparate electronic systems that must be synchronized in time with Intel® PTP Servo, which employs har…
- IEEE-1588 / PTP
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xSPI Multiple Bus Memory Controller
Synaptic Laboratories Ltd• HQ: GeorgiaThe industry ‘defacto standard’ memory controller for xSPI-like memories: HyperBus™ 1.0, 2.0 and 3.0 – OctaBus™ – Xccela® Bus – O…
- SPI / QSPI XSPI
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MAXVY Technologies Pvt Ltd• HQ: India
The I3C interface for the communication of an Smart Secure Platform(SSP), as defined in ETSI using the Smart Secure Platform Comm…
- I2C / I3C