Vendor: T2M GmbH Category: Video Processing

H.264/265 Video Encoder and Decoder IP

The Hardware Encoder Video Accelerator (HEVA), supports HEVC encoding low complexity with a flexible architecture targeting at le…

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Overview

The Hardware Encoder Video Accelerator (HEVA), supports HEVC encoding low complexity with a flexible architecture targeting at least 1080p60 with minimal processing units and memory cuts and
up to 2160p120 with large number of units and large memory cuts.
Trade-off performance/area at design configuration: Reference cache size for 2160p30 at 350 MHz, 1 reference frame and bandwidth, overhead of 100% for references i.e. 1.5 GBytes/sec (minimal is 1.2 GB/s)
Hardware interfaces :Host interface AXI3/AXI4 slave interface for the registers and command/status FIFO, Memory interface AXI3/AXI4 Streaming interfaces to External DRAM, Asynchronous AXI3/AXI4 128 bits interface, Synchronous DMA arbiter and memory interface
Task sequencing modules: Manages communication and storage between processing modules, Control the shared memories and caches between the TPU modules and TSU/MIF, Defines the execution mode of the task processing units
Task processing modules: Perform the pixel and bit-stream processing under control of TCR/TSU, The number of processing elements is defined at design configuration to sustain the required
performance, A local reference cache is needed for performance for some processing units.

Key features

  • Encoder acceleration
  • Performance up to 330 Mpixel/sec (2160p30 + 1080p30)
  • HEVC Main support, Level 4.2 (2160p30)
  • H.264 High Profile Progressive, Level 5.1 (2160p30, 1080p120)
  • HEVC Sample Adaptive Offset in-loop deblocking
  • Full coding unit support (from CU 64x64 to CU 8x8, PU 4x4)
  • No restriction on MV range allowed (X<8192, Y<4096)
  • Slice support: single slice or number of CTB lines per slice
  • Slice level IT programmable
  • Original input frame
  • Bottom/Right original padding on-the-fly
  • YUV 420 semi-planar: NV21
  • Reference frame usage
  • Internal 2D frame format
  • Optional proprietary lossless compression on reconstructed/reference frames
  • Up to two reference frames
  • Generalized P/B frames for low delay encoding
  • GOP up to 8 frames hierarchical B-frames for random access encoding
  • Motion vector range not limited, trade-off bandwidth versus MV range up to the application programming and design configuration.
  • Programmable quality/performance trade-off
  • Optional user defined input parameters
  • Deblocking slice parameters
  • User defined quantization scaling matrix tables
  • Chroma QP offsets
  • Region of interest input map table
  • Motion vector of Interest input map table
  • Optional user report output
  • Motion vector field
  • with/without Basic picture analysis
  • Latency tolerance at design configuration

Block Diagram

H.264/265 Video Encoder and Decoder IP block diagram

Applications

  • HEVC & H264 Recorder & Transcoder, for NAS application for Set Top Box application Best in Class HEVC Transcoder .
  • HEVC & H264 Video monitoring on video surveillance sequences –
  • On outdoor, non-static sequences ~5 to ~10% of bit-rate reduction
  • On outdoor, static sequences ~10 to 20% of bit-rate reduction
  • On indoor & lowlight sequences ~10% of bit-rate reduction

What’s Included?

  • RTL Source Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation & Design Guide
  • Verification Guide
  • Synthesis Guide

Specifications

Identity

Part Number
H.264/265 Video Encoder and Decoder IP
Vendor
T2M GmbH
Type
Silicon IP

Compute

Codec Standard
H.264 / AVC

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany
Contact T2M GmbH

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is H.264/265 Video Encoder and Decoder IP?

H.264/265 Video Encoder and Decoder IP is a Video Processing IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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